Patents Examined by Andrew Griffis
  • Patent number: 5215940
    Abstract: A method for looping the bond wires used to connected a semiconductor bond pad to a lead frame finger during bonding to improve the clearance between adjacent bond wires.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: June 1, 1993
    Inventors: John W. Orcutt, Randy O. Burrows
  • Patent number: 5169832
    Abstract: Metal boride powders can be produced with a predetermined particle size by controlling reaction conditions. The metal boride powder is produced by reacting a solid boron source, a metal source and a reductant under conditions sufficient to produce a metal boride powder with a particle size correlating to that of the solid boron source. The reaction is preferably stopped after the formation of products but before any apprecible crystal growth occurs.
    Type: Grant
    Filed: July 12, 1988
    Date of Patent: December 8, 1992
    Assignee: The Dow Chemical Company
    Inventors: Bijan Khazai, William G. Moore
  • Patent number: 5164336
    Abstract: A method of connecting a TAB tape to a semiconductor chip is disclosed which comprises the steps of preliminarily locating and fixing bumps at positions corresponding to a pattern of electrodes of the semiconductor chip to be connected; and bonding the bumps by thermocompression to the electrodes of the semiconductor chip and the leads of the TAB tape, respectively, so that each electrode of the semiconductor chip is electrically connected to the corresponding lead of the TAB tape through a corresponding one of the bumps. Also disclosed are a bump sheet and a bumped tape to be used in a method of connecting a TAB tape to a semiconductor chip.
    Type: Grant
    Filed: September 6, 1990
    Date of Patent: November 17, 1992
    Assignee: Nippon Steel Corporation
    Inventors: Yasuhide Ohno, Tadakatsu Maruyama, Hiroaki Otsuka, Hiroyuki Tanahashi
  • Patent number: 5155888
    Abstract: A wafer lifting apparatus is comprised of guide rails (10) that are disposed on a supporting surface (22). A lifting apparatus (24) is disposed on the surface (22), having an inclined surface (26). Grooves (28) are disposed on the inclined surface and spaced apart a distance equal to that of wafers (20) in a wafer handling boat (16). The wafer handling boat (16) has the end pieces (12) and (14) urged downward into the guide rails (10) until the lowermost peripheral edges of the wafers (20) contact the grooves (28) in the inclined surface (26). When fully lowered, the rearmost ones of the wafers (20) are completely lifted out of the boat such that they are supported entirely by the grooves (28). In this manner, they can be viewed from the end of the wafer lifting apparatus. A flat finding device in the form of a flat finding cylinder (44) is also provided in an opening (38) on a supporting surface (36) for holding the boat (16).
    Type: Grant
    Filed: May 22, 1991
    Date of Patent: October 20, 1992
    Assignee: Mactronix
    Inventor: John J. Lau
  • Patent number: 5156983
    Abstract: This invention involves the selective plating of the outer leads in tape automated bonding section (TAB section). An inner and an outer gasket are mounted over, respectively, an inner and an outer portion of the outer leads and a voltage is applied to a common plane conductor. A barrier material, usually nickel, is applied to the outer leads protruding between the inner and the outer leads and then solder is applied over the nickel layer. The debus areas which connect all the outer leads to the common plane conductor are then excised from the TAB section which is now ready for final test.
    Type: Grant
    Filed: October 26, 1989
    Date of Patent: October 20, 1992
    Assignee: Digtial Equipment Corporation
    Inventors: Randall L. Schlesinger, Ralph W. Doe, Richard D. Gates, Dennis P. Goddard, Shih C. Hsu
  • Patent number: 5146661
    Abstract: An apparatus and method for loading integrated circuit packages into package carriers is disclosed. Featured is a pick-and-place mechanism mounted on a tiltable table. Packages and carriers slide toward the pick-and-place mechanism under the influence of gravity. The pick-and-place mechanism combines the packages with carriers. The package/carrier combinations then slide away from the pick-and-place mechanism.
    Type: Grant
    Filed: November 7, 1990
    Date of Patent: September 15, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Jonathan D. Knepper, Gerald J. Masavage, Phillip A. Solomon
  • Patent number: 5147822
    Abstract: An electronic device comprising a substrate having a frame, a metal lead and electronic parts in a bonding structure, and a molding of an organic resin formed on the substrate, wherein the surface of the organic resin is provided with a hardened water-resistant or carbonaceous film.
    Type: Grant
    Filed: February 25, 1991
    Date of Patent: September 15, 1992
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsunori Tsuchiya, Kazuo Urata, Itaru Koyama, Shinji Imatou, Shigenori Hayashi, Naoki Hirose, Mari Sasaki, Noriya Ishida, Kouhei Wada
  • Patent number: 5139974
    Abstract: A semiconductor manufacturing process for increasing the optical absorptivity and decreasing the optical reflectivity of a metal film in order to reduce the effect of reflective notching and widen the process exposure window for photolithographic patterning. A metal film to be photopatterned is first deposited on a substrate and is then roughened to increase the surface area and to provide an irregular surface for reabsorbing scattered light. Surface roughening may be accomplished by dry etching or by simple ion bombardment during a reverse sputtering process. A second metal layer may also be deposited upon the roughened surface by sputter deposition to achieve a desired surface roughness.
    Type: Grant
    Filed: January 25, 1991
    Date of Patent: August 18, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Chang Yu, Yauh-Ching Liu
  • Patent number: 5135887
    Abstract: A simple effective and fairly stable boron source that is easy to prepare and simple to operate under UHV processing conditions is disclosed. The method for fabricating this boron source includes the in situ alloying of boron into a high melting point elemental semiconductor material, preferably silicon, in the hearth of an electron beam evaporator. A supersaturated solution of boron in silicon is created by melting the silicon and dissolving the boron into it and quenching the solution. The boron needs to be of high purity and may be in the form of crystalline granules for this to take place under controlled conditions and moderate power levels. When silicon is evaporated from this resultant silicon-boron alloy source, the silicon evaporates uncontaminated from a molten pool of the alloy in the center of the hearth. A segregation of boron into the liquid phase occurs and a segregation takes place from this molten phase into the vapor phase that is being evaporated from the pool.
    Type: Grant
    Filed: June 10, 1991
    Date of Patent: August 4, 1992
    Assignee: International Business Machines Corporation
    Inventors: Sylvain L. Delage, Bruce A. Ek, Subramanian S. Iyer
  • Patent number: 5130110
    Abstract: Process for obtaining by sol-gel route refractory metal oxides based on silica in which a monolithic gel is prepared, in an aqueous medium, at a temperature of less than 60.degree. C., by leaving at rest an aqueous sol obtained by simple mixing in stoichiometric quantities of an aqueous sol of silicic acid and of one or more aqueous solutions of a water-soluble salt of one or more other constitutive metals of these oxides, then the monolithic gel obtained is calcined at a temperature of less than 1000.degree. C. after it has been dried at a temperature of less than 150.degree. C.
    Type: Grant
    Filed: December 18, 1990
    Date of Patent: July 14, 1992
    Assignee: Societe Francaise Hoechst
    Inventors: Patrice Rouet, Florence Syoen
  • Patent number: 5128279
    Abstract: Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: July 7, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: Subhash R. Nariani, Dipankar Pramanik
  • Patent number: 5122479
    Abstract: Disclosed is a method of making a Si-based semiconductor device comprising a contact region that comprises a thin (exemplarily less than 50 nm), substantially uniform silicide layer. The silicide preferably is CoSi.sub.2 or TiSi.sub.2. The method comprises implantation of the appropriate metal ions into a Si body, the dose and the body temperature selected such that substantially complete amorphization of the implant volume results. Subsequently, the Si body is subjected to an annealing treatment that results in recrystallization of the implant volume and formation of the silicide layer. The layer extends to the surface of the body and contains essentially all of the implanted metal ions. The invention can advantageously be used in conjunction with extremely shallow junctions, such as will be of interest in short (e.g., <0.5 .mu.m) channel CMOS devices.
    Type: Grant
    Filed: April 11, 1991
    Date of Patent: June 16, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Sarah A. Audet, Conor S. Rafferty, Kenneth T. Short, Alice E. White
  • Patent number: 5120678
    Abstract: An improved method is provided for assembling an integrated circuit component to a substrate by a solder bump interconnection that is reinforced by a polymer film. The component is attached to a region of the substrate by a plurality of solder bump interconnections that create a gap between the component interface and the substrate region. A polymer dam is applied to the region encircling the attached component spaced apart therefrom. A liquid polymer precursor material is applied to the region including the gap and is confined by the dam to prevent indiscriminate flow across the substrate. In one aspect of this invention, gas is vented from the gap through a passage in the substrate to enhance fill by the precursor liquid. In another aspect of this invention, the precursor liquid is injected into the gap through a passage in the substrate and spread outwardly therefrom.
    Type: Grant
    Filed: November 5, 1990
    Date of Patent: June 9, 1992
    Assignee: Motorola Inc.
    Inventors: Kevin D. Moore, Steven C. Machuga, John W. Stafford, Kenneth Cholewczynski, Dennis B. Miller
  • Patent number: 5116785
    Abstract: A method for forming a layer of a Group II or III fluoride on a semiconductor substrate (e.g. as epitaxial insulating layer) comprising vaporizing a precursor (I), where M is Be, Ca, Sr, Ba or lanthanide, b and d are 0 or 1. A, B, C and D are independently (IIA) or (IIB), X being O, S, NR, PR where R is H, alkyl, perfluoroalkyl; Y is perfluoroalkyl, fluoroalkenyl, fluoroalkylamine or fluoroalkenylamine; Z is H, F, alkyl, perfluoroalkyl or perfluoroalkenyl; and then decomposing the precursor vapor to form M fluoride. A preferred precursor for calcium fluoride is calcium 1,1,1,5,5,5-hexafluor-2,4-pentanedione complex where b and d are 0.
    Type: Grant
    Filed: November 30, 1990
    Date of Patent: May 26, 1992
    Assignee: The Secretary of State for Defence in her Britannic Majesty's Government of The United Kingdom of Great Britian and Northern Ireland
    Inventors: Kevin J. Mackey, Anthony W. Vere, Donald C. Bradley, Dario M. Frigo, Marc M. Faktor, deceased
  • Patent number: 5115545
    Abstract: An apparatus for connecting a semiconductor device having multi-electrodes at small pitches to a wiring board in such a manner as to secure the alignment between the electrodes and the wiring patterns, the chips being secured to the wiring board with an insulating resin of a photo-setting nature. The apparatus eliminates the necessity of using heat or supersonic waves, thereby reducing equipment costs.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: May 26, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Kenzo Hatada, Yoshinobu Takeshita, Kazuya Otani, Kimiaki Takeda
  • Patent number: 5116783
    Abstract: A method of producing a semiconductor device includes bonding a semiconductor chip to a die pad of a lead frame by means of a silicone resin, to bonding a copper wire and an aluminum electrode of the semiconductor chip in such a manner that intermetallic compound mainly consisting of CuAl.sub.2 is formed in the bonding region. This method suppresses the deterioration of the copper-aluminum alloy layer and these semiconductor devices have a high reliability at a high temperature, as well as uniform quality in the production.
    Type: Grant
    Filed: August 11, 1989
    Date of Patent: May 26, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kiyoaki Tsumura
  • Patent number: 5114878
    Abstract: A method of bonding bumps to leads of a TAB tape comprises the steps of preparing a substrate which is provided with through-holes, each having a size which will not allow the bumps to pass therethrough, at positions corresponding to bonding positions of the leads of the TAB tape where the bumps are to be bonded; provisionally arranging the bumps at positions of the through-holes at one side of the substrate by reducing a pressure in another side of the substrate opposite to said one side thereof to such the bumps in said through-holes; disposing the substrate on which the bumps are provisionally arranged and said TAB tape in such a positional relationship that said bumps face to the bonding positions of the leads of said TAB tape; and bonding the provisionally arranged bumps to the leads at the bonding positions and an apparatus for arranging bumps in a positional relationship corresponding to bonding positions of leads of a TAB tape.
    Type: Grant
    Filed: March 13, 1991
    Date of Patent: May 19, 1992
    Assignee: Nippon Steel Corporation
    Inventors: Tadakatsu Maruyama, Yasuhide Ohno, Masashi Konda, Tosiharu Kikuchi, Yasuhiro Suzuki, Tomohiro Uno, Hiroaki Otsuka, Hiroyuki Tanahashi
  • Patent number: 5110761
    Abstract: An improved contact is obtained to power devices having a raised dielectric region adjacent the die contact region by providing a contact dimple on the otherwise flat metal lead used for die contact. The dimple is arranged above the die contact and soldered thereto. The radius of curvature and depth of the dimple is adjusted so that the contact lead is far enough away from the edge of the surrounding raised dielectric at the edge of the die contact to provide a laterally concave outward air-solder interface in that location. This prevents solder creep onto the dielectric surface and avoids die edge shorting. Several dimple shapes are described.
    Type: Grant
    Filed: February 12, 1990
    Date of Patent: May 5, 1992
    Assignee: Motorola, Inc.
    Inventors: Martin Kalfus, Eugene L. Foutz
  • Patent number: 5108962
    Abstract: A composition and method for producing boron carbide/titanium diboride composite ceramic powders is disclosed. The process comprises the ordered steps of (a) intimately mixing as reactants boron carbide and a titanium source, such that the average reactant particle size is less than about 20 microns and substantially all discrete reactant areas are less than about 50 microns, and (b) reacting the product of step (a) under conditions sufficient to produce a boron carbide/titanium diboride composite ceramic powder wherein at least a portion of the boron carbide particles form substrates to which at least a portion of the titanium diboride particles are attached. The method can be used to produce a composite ceramic powder having boron carbide and titanium diboride particles less than about 20 microns in diameter.
    Type: Grant
    Filed: May 26, 1988
    Date of Patent: April 28, 1992
    Assignee: The Dow Chemical Company
    Inventors: Bijan Khazai, William G. Moore
  • Patent number: 5102832
    Abstract: A process for texturization of polycrystalline silicon comprising the steps of preparing the wafer surface prior to poly deposition with a material which will cause the poly to preferentially nucleate during deposition and form poly nodules on the wafer surface. Polysilicon will continue to coat the previously created poly nodules throughout poly deposition, thereby resulting in a stable, texturized polysilicon structure.
    Type: Grant
    Filed: February 11, 1991
    Date of Patent: April 7, 1992
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle