Patents Examined by Andrew Q. Tran
  • Patent number: 11177371
    Abstract: A method is provided for fabricating a double gate structure for transistors with superposed bars, including: providing, on a support, a stack including an alternation of one or several first bars based on a first semiconducting material, and one or several second bars based on a second semiconducting material; removing lateral portions of the second bars; forming insulating plugs in contact with lateral regions of the second bars; removing the first bars; and forming a gate electrode facing an upper face and a lower face of the second bars, the insulating plugs being arranged in contact with the lateral regions of the second bars when the gate electrode is being formed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: November 16, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Shay Reboh
  • Patent number: 11158666
    Abstract: A multi-wavelength light-emitting diode epitaxial structure comprises of a substrate and at least three light-emitting elements, wherein the light-emitting elements are sequentially stacked on the substrate. For each two adjacent light-emitting elements, the light-emitting element disposed closer to the light-exiting surface has a higher bandgap than that of the light-emitting element disposed farther from the light-exiting surface. Each of the light-emitting elements comprises of an active layer and two cladding layers disposed on two opposite sides of the active layer, and each active layer includes a multiple quantum well structure. Cladding layers of different refractive indexes are arranged incrementally from the substrate to the light-exiting surface. Any given two adjacent cladding layers from two light-emitting elements have a combined thickness of 1 ?m or less. The emission wavelengths of the light-emitting elements are ultraviolet or infrared bands.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: October 26, 2021
    Assignee: EPILEDS TECHNOLOGIES, INC.
    Inventors: Jiun-Wei Tu, Wei-Yu Tseng, Tetsuya Gouda
  • Patent number: 11127928
    Abstract: A display device includes: a display panel to display an image; an optical film over the display panel and including at least one phase retarder and a polarizer; a first adhesive layer between the display panel and the optical film and contacting a first surface of the optical film; and a second adhesive layer on the optical film and contacting a second surface of the optical film opposite the first surface, and the first adhesive layer and the second adhesive layer contact each other.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 21, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Heeyoung Lee, Inseo Kee, Jinkyu Kim, Hansun Ryou
  • Patent number: 11114628
    Abstract: A method of manufacturing flexible OLED display panel is provided. The method comprises following steps. Providing a glass carrier, sequentially forming a flexible substrate, a low temperature poly-Si layer and OLED element layer on a surface of the glass carrier; forming a planar layer on a second surface of the glass carrier which is away from the flexible substrate and obtaining a planning OLED display panel; removing the glass carrier by laser lift-off the planning OLED display panel and obtaining the flexible OLED display panel. The method could reduce the problem of lower peeling successful rate caused by the unevenly distributing in the flexible substrate during the laser lift-off process.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 7, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiang Jin
  • Patent number: 11101249
    Abstract: In an embodiment, a multi-chip module includes a first carrier including a mold material and at least two light-emitting diode chips embedded at least by side faces in the first carrier, wherein the light-emitting diode chips have first electrical contacts on a front side and second electrical contacts on a rear side, wherein the front side is configured as a radiation side, wherein the first electrical contacts are connected to control lines, wherein the control lines are arranged on a front side of the first carrier, wherein the second electrical contacts are connected to a collective line, and wherein the collective line is led to a rear side of the first carrier.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 24, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Frank Singer, J├╝rgen Moosburger, Thomas Schwarz, Lutz Hoeppel, Matthias Sabathil
  • Patent number: 11087991
    Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Eric Freeman, Paolo Tessariol
  • Patent number: 11075210
    Abstract: A circular printed memory device and a method for fabricating the circular printed memory device are disclosed. For example, the circular printed memory device includes a base substrate, a plurality of bottom electrodes arranged in a circular pattern on the base substrate, a ferroelectric layer on top of the plurality of bottom electrodes and a single top electrode on the ferroelectric layer that contacts each one of the plurality of bottom electrodes via the ferroelectric layer.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: July 27, 2021
    Assignee: Xerox Corporation
    Inventors: Christopher David Blair, Markus R. Silvestri
  • Patent number: 11075192
    Abstract: A diode including: first and second doped semi-conductor portions forming a p-n junction, a first part of the first portion being arranged between a second part of the first portion and the second portion; dielectric portions covering side walls of the second portion and the first part of the first portion; a first electrode arranged against outer side walls of the dielectric portions and against side walls of the second part of the first portion, electrically connected to the first portion only by contact with said side walls, and passing through the entire thickness of the first portion; a second optically reflecting electrode electrically connected to the second portion such that the second portion is arranged between the second electrode and the first portion.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 27, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Hubert Bono, Jonathan Garcia, Ivan-Christophe Robin
  • Patent number: 11031430
    Abstract: An image sensor and an electronic apparatus, the image sensor including a plurality of pixels, each pixel of the plurality of pixels including a photodiode and a transfer transistor, a reset transistor, a source-follower transistor, and a selection transistor, which correspond to the photodiode; a plurality of first interconnection lines connected to gates of the transfer transistor, the reset transistor, and the selection transistor, the plurality of first interconnection lines extending in a first direction; and a plurality of second interconnection lines connected to a source region of the selection transistor, the plurality of second interconnection lines extending in a second direction that intersects the first direction, wherein the plurality of second interconnection lines includes dummy lines on a peripheral area that is outside of a pixel area in which the pixels are located.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-kyu Lee, Young-chan Kim, Seung-sik Kim
  • Patent number: 11031387
    Abstract: A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10930621
    Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: February 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Rahul Agarwal, Milind S. Bhagavat
  • Patent number: 10930716
    Abstract: An electroluminescent display device includes a substrate, an electrode on the substrate, a first bank layer for covering an end of the electrode and exposing the electrode, a second bank layer on the first bank layer, and an emission layer on the exposed electrode, wherein the first bank layer includes a first pattern portion for covering the end of the electrode, and a second pattern portion upwardly extending from the first pattern portion.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 23, 2021
    Assignee: LG Display Co. Ltd.
    Inventors: Hyunil Ko, HongKi Park
  • Patent number: 10923505
    Abstract: The present disclosure provides a display substrate, a fabricating method thereof, and a display device. The method includes forming a light shielding layer on a surface of a base substrate, and forming a plurality of thin film transistors on a side of the light shielding layer away from the base substrate. Forming a plurality of thin film transistors on a side of the light shielding layer away from the base substrate includes forming a semiconductor layer at a position where an active layer is to be formed in each of the plurality of thin film transistors, generating heat using the light shielding layer, and utilizing the heat to crystallize the semiconductor layer.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Guan, Lu Wang, Woobong Lee, Jianhua Du, Yang Lv, Zhaohui Qiang, Guangcai Yuan
  • Patent number: 10916689
    Abstract: A light emitting device comprises a reflector cup coupled to a base that defines a cavity. The base comprises a plurality of metal pads exposed on a bottom surface of the cavity. The base further comprises a plurality of protrusions arranged around a perimeter of the base and disposed inside one or more side surfaces of the reflector cup. The light emitting device comprises an LED die disposed over the bottom surface of the cavity. The LED die is coupled to the metal pads with gold-tin solder. The LED die has a footprint that is at most 30% smaller than an area of a top opening of the cavity.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 9, 2021
    Assignee: Lumileds LLC
    Inventors: Sridevi A. Vakkalanka, S. Rao Peddada
  • Patent number: 10892378
    Abstract: A method is provided for obtaining a semi-polar nitride layer obtained from a gallium and nitrogen based material on an upper surface of a crystalline substrate of cubic symmetry, including: etching parallel grooves from the upper surface having two opposed inclined facets, one having a crystalline orientation <111>; forming a mask above the upper surface such that the facets having <111> orientation are not masked; and then forming the layer by epitaxial growth from the non-masked facets, including: a first epitaxial growth phase to form a seed in parallel grooves; interrupting the first phase when the seed has an inclined facet having a crystalline orientation 0001 and an upper facet having a crystalline semi-polar orientation 1011; a surface treatment step including modifying an upper portion of the seed to include silicon; and a second epitaxial growth phase from the inclined facet, continuing until coalescence of seeds of adjacent parallel grooves.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 12, 2021
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Guy Feuillet, Michel El Khoury Maroun, Philippe Vennegues, Jesus Zuniga Perez
  • Patent number: 10879201
    Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Shou-Yi Wang, Tsung-Shu Lin
  • Patent number: 10873007
    Abstract: A light-emitting device includes a package and a light-emitting element. The package includes a pair of leads each including a main body portion and an extension portion, a resin portion holding the pair of leads, and a concave portion having a bottom surface where an upper surface of each of the pair of leads is exposed. The extension portion extends from an outer edge of the main body portion to an outer surface of the package. The light-emitting element is mounted at the bottom surface of the concave portion. The main body portion has a trench and a through-hole in a portion of the main body portion buried in a sidewall of the concave portion. The through-hole is continuous with the trench. When viewed in top-view, the through-hole is provided inward of the outer edge of the main body portion at a vicinity of the extension portion.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 22, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Ryosuke Wakaki
  • Patent number: 10867795
    Abstract: A method of etching a hardmask layer formed on a substrate is provided. The method includes supplying an etching gas mixture to a processing region of a processing chamber. A device is disposed in the processing region when the etching gas mixture is supplied to the processing region. The device comprises a substrate and a hardmask layer formed over the substrate. The etching gas mixture comprises a fluorine-containing gas, a silicon-containing gas, and an oxygen-containing gas. The method further includes providing RF power to the etching gas mixture to form a plasma in the processing region. The plasma is configured to etch exposed portions of the hardmask layer.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 15, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Nancy Fung, Gene Lee, Hailong Zhou, Zohreh Hesabi, Akhil Mehrotra, Shan Jiang, Abhijit Patil, Chi-I Lang, Larry Gao
  • Patent number: 10862056
    Abstract: A display device including: a flexible substrate having a first surface and a second surface opposite the first surface; a display unit arranged on the first surface of the flexible substrate; and a lower protective film arranged on the second surface and including a base film, an adhesive layer arranged on one side of the base film, a light-shielding layer arranged on the other side of the base film, and a conductive material layer interposed between the base film and the light-shielding layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sungjune Park, Jinkyu Kim
  • Patent number: 10854553
    Abstract: A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shun-Tsat Tu, Chunku Kuo, Ya-Tian Hou, Tsung-Chieh Kuo