Patents Examined by Andrew Q. Tran
  • Patent number: 10892378
    Abstract: A method is provided for obtaining a semi-polar nitride layer obtained from a gallium and nitrogen based material on an upper surface of a crystalline substrate of cubic symmetry, including: etching parallel grooves from the upper surface having two opposed inclined facets, one having a crystalline orientation <111>; forming a mask above the upper surface such that the facets having <111> orientation are not masked; and then forming the layer by epitaxial growth from the non-masked facets, including: a first epitaxial growth phase to form a seed in parallel grooves; interrupting the first phase when the seed has an inclined facet having a crystalline orientation 0001 and an upper facet having a crystalline semi-polar orientation 1011; a surface treatment step including modifying an upper portion of the seed to include silicon; and a second epitaxial growth phase from the inclined facet, continuing until coalescence of seeds of adjacent parallel grooves.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 12, 2021
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Guy Feuillet, Michel El Khoury Maroun, Philippe Vennegues, Jesus Zuniga Perez
  • Patent number: 10879201
    Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Shou-Yi Wang, Tsung-Shu Lin
  • Patent number: 10873007
    Abstract: A light-emitting device includes a package and a light-emitting element. The package includes a pair of leads each including a main body portion and an extension portion, a resin portion holding the pair of leads, and a concave portion having a bottom surface where an upper surface of each of the pair of leads is exposed. The extension portion extends from an outer edge of the main body portion to an outer surface of the package. The light-emitting element is mounted at the bottom surface of the concave portion. The main body portion has a trench and a through-hole in a portion of the main body portion buried in a sidewall of the concave portion. The through-hole is continuous with the trench. When viewed in top-view, the through-hole is provided inward of the outer edge of the main body portion at a vicinity of the extension portion.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 22, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Ryosuke Wakaki
  • Patent number: 10867795
    Abstract: A method of etching a hardmask layer formed on a substrate is provided. The method includes supplying an etching gas mixture to a processing region of a processing chamber. A device is disposed in the processing region when the etching gas mixture is supplied to the processing region. The device comprises a substrate and a hardmask layer formed over the substrate. The etching gas mixture comprises a fluorine-containing gas, a silicon-containing gas, and an oxygen-containing gas. The method further includes providing RF power to the etching gas mixture to form a plasma in the processing region. The plasma is configured to etch exposed portions of the hardmask layer.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 15, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Nancy Fung, Gene Lee, Hailong Zhou, Zohreh Hesabi, Akhil Mehrotra, Shan Jiang, Abhijit Patil, Chi-I Lang, Larry Gao
  • Patent number: 10862056
    Abstract: A display device including: a flexible substrate having a first surface and a second surface opposite the first surface; a display unit arranged on the first surface of the flexible substrate; and a lower protective film arranged on the second surface and including a base film, an adhesive layer arranged on one side of the base film, a light-shielding layer arranged on the other side of the base film, and a conductive material layer interposed between the base film and the light-shielding layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sungjune Park, Jinkyu Kim
  • Patent number: 10854553
    Abstract: A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shun-Tsat Tu, Chunku Kuo, Ya-Tian Hou, Tsung-Chieh Kuo
  • Patent number: 10847591
    Abstract: A display panel according to an embodiment of the inventive concept includes a base substrate on which a pixel area and a surrounding area adjacent to the pixel area are defined, a pixel defining layer which is disposed on the base substrate and on which a plurality of openings corresponding to the pixel area are defined, and a plurality of light emitting layers disposed in the plurality of openings, respectively. Here, the pixel defining layer includes a first pixel defining portion, a second pixel defining portion disposed between the light emitting layers and the first pixel defining portion, and a third pixel defining portion that covers the first pixel defining portion and the second pixel defining portion and includes a spaced portion that exposes a portion of the first pixel defining portion.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: November 24, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Geuntak Kim
  • Patent number: 10847485
    Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 10847498
    Abstract: A display panel includes a plurality of light-emitting elements. Light emitted from a first light-emitting element has a CIE 1931 chromaticity coordinate x of greater than 0.680 and less than or equal to 0.720 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.260 and less than or equal to 0.320. Light emitted from a second light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.130 and less than or equal to 0.250 and a CIE 1931 chromaticity coordinate y of greater than 0.710 and less than or equal to 0.810. Light emitted from a third light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.120 and less than or equal to 0.170 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.020 and less than 0.060.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 24, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daiki Nakamura, Yusuke Nishido, Satoshi Seo, Toshiki Sasaki, Ryohei Yamaoka, Akihiro Kaita
  • Patent number: 10840177
    Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Tin Poay Chuah
  • Patent number: 10840284
    Abstract: The present technology relates to an imaging element and an imaging device that enables reduction of a distance measurement error. The device includes a pixel array unit including a plurality of pixels that performs photoelectric conversion of light, in which each includes: a substrate that performs photoelectric conversion of the light; a first signal extraction portion including an application electrode to generate an electric field by application of a voltage and an attraction electrode to detect a signal carrier generated by photoelectric conversion; a second signal extraction portion including the application electrode and the attraction electrode; and a converging portion that is formed on the substrate and causes the light to enter the substrate. The converging portion converges the light at least between the first signal extraction portion and the second signal extraction portion provided in the substrate. The present technology can be applied to a CAPD sensor.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 17, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kohei Ennoji, Shingo Yamaguchi
  • Patent number: 10840230
    Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventor: Edward A. Burton
  • Patent number: 10840408
    Abstract: The present invention provides light-emitting devices with improved quantum efficiency. The light emitting diode structure comprising: a p-doped layer, an n-doped layer; and a multiple quantum well structure sandwiched between the p-doped layer and n-doped layer, wherein the multiple quantum well structure comprising a quantum well disposed between n-doped barrier layers.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 17, 2020
    Assignee: VueReal Inc.
    Inventors: Jian Yin, Dayan Ban, Ehsanollah Fathi, Gholamreza Chaji
  • Patent number: 10840412
    Abstract: A semiconductor light emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, a first transparent electrode layer on the second conductivity-type semiconductor layer, a first insulating layer on the first transparent electrode layer, the first insulating layer including a plurality of through-holes, a reflective electrode layer on the first insulating layer and connected to the first transparent electrode layer through the plurality of through-holes, and a transparent protection layer covering upper and side surfaces of the reflective electrode layer, the transparent protection layer being on a portion of the first insulating layer.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Heon Yoon, Jung Hwan Kil, Tae Hun Kim, Hwa Ryong Song, Jae In Sim
  • Patent number: 10840317
    Abstract: A display apparatus includes a substrate including a display area and a sensor area, the display area including main pixels and the sensor area including auxiliary pixels and a transmission portion; a first pixel electrode and a first emission layer in each of the main pixels; a second pixel electrode and a second emission layer in each of the auxiliary pixels; an opposite electrode integrally arranged in the display area and the sensor area; and a metal layer at least partially surrounding the transmission portion, wherein the opposite electrode has an opening corresponding to the transmission portion.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 17, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eonseok Oh, Woosik Jeon, Sangyeol Kim
  • Patent number: 10840418
    Abstract: Systems and methods for fabricating parabolic LEDs are provided. The parabolic shape of the LEDs is precisely-controlled and highly-uniform across a substrate. By precisely controlling the shape, and providing a high-uniformity across the substrate, the luminance and process yield of the LEDs is enhanced. The precise-control and high-uniformity of the shape is enabled via a precisely-shaped and highly-uniform mask formed on the substrate. The ability to precisely-control both the shape and uniformity the mask is achieved by forming the mask utilizing three-dimensional (3D) patterning and/or machining methods. The mask includes a precisely-shaped boss with the same shape as the LED, and a cylindrical protrusion extending beyond the boss. The combination of the boss and cylindrical protrusion allows for the mask to be over-etched, without significantly effecting the shape of the LED. Thus, any non-uniformities etching process do not decrease the luminance, nor uniformity, of the LEDs.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: David Massoubre, Daniel Brodoceanu, Oscar Torrents Abad, Vaishali Chopra
  • Patent number: 10825844
    Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 3, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Hyun Choung, Jae Uoon Kim
  • Patent number: 10825774
    Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Juhyeon Oh, Sunchul Kim, Hyunki Kim
  • Patent number: 10784190
    Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
  • Patent number: 10784158
    Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 22, 2020
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez