Abstract: A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up over and electrically coupled to at least one of the conductive structures. An integrated circuit is disposed over the first surface and electrically coupled to the conductive structures. A molding compound is formed over the first surface of the substrate.

Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.

Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.

Abstract: A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.

Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

Abstract: The present disclosure relates a method of forming substrate identification marks. In some embodiments, the method may be performed by forming a photosensitive material over a substrate. A first type of electromagnetic radiation is selectively provided to the photosensitive material to expose a plurality of substrate identification marks within the photosensitive material, and a second type of electromagnetic radiation is selectively provided to the photosensitive material to expose one or more alignment marks within the photosensitive material. Exposed portions of the photosensitive material are removed to form a patterned photosensitive material. The substrate is etched according to the patterned photosensitive material to form recesses within the substrate that are defined by the plurality of substrate identification marks and the one or more alignment marks.

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

Abstract: In some embodiments, the present disclosure relates a lithographic substrate marking tool. The lithographic substrate marking tool has a first lithographic exposure tool arranged within a shared housing and configured to generate a first type of electromagnetic radiation during a plurality of exposures. A mobile reticle has a plurality of different reticle fields respectively configured to block a portion of the first type of electromagnetic radiation to expose a substrate identification mark within a photosensitive material overlying a semiconductor substrate. A transversal element is configured to move the mobile reticle so that separate ones of the plurality of reticle fields are exposed onto the photosensitive material during separate ones of the plurality of exposures.

Abstract: A light-emitting diode chip includes a semiconductor layer sequence based on InGaAlAsP and generates visible light or near-infrared radiation, a current spreading layer located directly on the semiconductor layer sequence and based on AlGaAs, an encapsulation layer applied directly to at least one of the current spreading layer and the semiconductor layer sequence and has an average thickness of 10 nm to 200 nm and a defect density of at most 10/mm2, at least one cover layer applied directly to the encapsulation layer at least in places, at least one non-metallic reflection layer located in places on a side of the current spreading layer facing away from the semiconductor layer sequence and covered in places by the encapsulation layer, and at least one of a mirror layer and an adhesion-promoting layer arranged in places on a side of the reflection layer facing away from the current spreading layers.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. According to an embodiment, a method includes: providing a semiconductive substrate; forming a doped region in the semiconductive substrate; forming a trench in the doped region; forming a capacitor in the trench, the capacitor comprising alternatingly arranged electrodes and dielectric layers; depositing a first dielectric material in the trench and over the capacitor; etching the first dielectric material to form a spacer on a sidewall of a topmost dielectric layer of the capacitor; and depositing a core portion in the trench and laterally surrounded by the spacer.

Abstract: Provided are a perovskite light emitting device containing an exciton buffer layer, and a method for manufacturing the same. A light emitting device of the present invention comprises: an exciton buffer layer in which a first electrode, a conductive layer disposed on the first electrode and comprising a conductive material, and a surface buffer layer containing fluorine-based material having lower surface energy than the conductive material are sequentially deposited; a light-emitting layer disposed on the exciton buffer layer and containing an organic-inorganic hybrid perovskite light emitting body; and a second electrode disposed on the light-emitting layer.

Abstract: A method for manufacturing a SiC epitaxial wafer according to one aspect of the present invention includes separately introducing, into a reaction space for SiC epitaxial growth, a basic N-based gas composed of molecules containing an N atom within the molecular structure but having neither a double bond nor a triple bond between nitrogen atoms, and a Cl-based gas composed of molecules containing a Cl atom within the molecular structure, and mixing the N-based gas and the Cl-based gas at a temperature equal to or higher than the boiling point or sublimation temperature of a solid product generated by mixing the N-based gas and the Cl-based gas.

Abstract: In an embodiment the optical component includes an optoelectronic semiconductor chip including a radiation emission face, a deflection element configured to deflect electromagnetic radiation emitted by the optoelectronic semiconductor chip in a main emission direction which forms an angle deviating from 90° with the radiation emission face, wherein the deflection element is configured as a prism structure and an optical lens having an optical axis, wherein the optical axis forms an angle deviating from 90° with the radiation emission face.

Abstract: A semiconductor light emitting device includes a substrate having a first major surface and a second major surface, a semiconductor layer that includes a first semiconductor layer of a first conductive type formed on the first major surface of the substrate, a light emitting layer formed on the first semiconductor layer and a second semiconductor layer of a second conductive type formed on the light emitting layer, and a mesa structure formed in the semiconductor layer by selectively notching the first semiconductor layer, the light emitting layer and the second semiconductor layer so as to expose the first semiconductor layer, and a ratio of a luminescent area of the light emitting Layer with respect to an area of the first major surface of the substrate being set to equal to or smaller than 0.25.

Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

Abstract: A photonic quantum memory is provided. The photonic quantum memory includes entanglement basis conversion module configured to receive a first polarization-entangled photon pair and to produce a second entangled photon pair. The second polarization-entangled photon pair can be a time-bin entangled or a propagation direction-entangled photon pair. The photonic quantum memory further includes a photonic storage configured to receive the second entangled photon pair from the basis conversion module and to store the second entangled photon pair.

Abstract: A method of forming a vertical transport fin field effect transistor (VT FinFET), including, forming a plurality of vertical fins on a substrate, forming a sacrificial liner on at least two of the plurality of vertical fins, forming sidewall spacers on the vertical surfaces of the sacrificial liner, wherein the sidewall spacers are on opposite sides of the at least two of the plurality of vertical fins, and removing a portion of the sacrificial liner to form an l-shaped channel adjacent to each of the at least two of the plurality of vertical fins.