Abstract: A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.

Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

Abstract: A display panel includes a plurality of light-emitting elements. Light emitted from a first light-emitting element has a CIE 1931 chromaticity coordinate x of greater than 0.680 and less than or equal to 0.720 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.260 and less than or equal to 0.320. Light emitted from a second light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.130 and less than or equal to 0.250 and a CIE 1931 chromaticity coordinate y of greater than 0.710 and less than or equal to 0.810. Light emitted from a third light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.120 and less than or equal to 0.170 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.020 and less than 0.060.

Abstract: A display panel according to an embodiment of the inventive concept includes a base substrate on which a pixel area and a surrounding area adjacent to the pixel area are defined, a pixel defining layer which is disposed on the base substrate and on which a plurality of openings corresponding to the pixel area are defined, and a plurality of light emitting layers disposed in the plurality of openings, respectively. Here, the pixel defining layer includes a first pixel defining portion, a second pixel defining portion disposed between the light emitting layers and the first pixel defining portion, and a third pixel defining portion that covers the first pixel defining portion and the second pixel defining portion and includes a spaced portion that exposes a portion of the first pixel defining portion.

Abstract: The present technology relates to an imaging element and an imaging device that enables reduction of a distance measurement error. The device includes a pixel array unit including a plurality of pixels that performs photoelectric conversion of light, in which each includes: a substrate that performs photoelectric conversion of the light; a first signal extraction portion including an application electrode to generate an electric field by application of a voltage and an attraction electrode to detect a signal carrier generated by photoelectric conversion; a second signal extraction portion including the application electrode and the attraction electrode; and a converging portion that is formed on the substrate and causes the light to enter the substrate. The converging portion converges the light at least between the first signal extraction portion and the second signal extraction portion provided in the substrate. The present technology can be applied to a CAPD sensor.

Abstract: Systems and methods for fabricating parabolic LEDs are provided. The parabolic shape of the LEDs is precisely-controlled and highly-uniform across a substrate. By precisely controlling the shape, and providing a high-uniformity across the substrate, the luminance and process yield of the LEDs is enhanced. The precise-control and high-uniformity of the shape is enabled via a precisely-shaped and highly-uniform mask formed on the substrate. The ability to precisely-control both the shape and uniformity the mask is achieved by forming the mask utilizing three-dimensional (3D) patterning and/or machining methods. The mask includes a precisely-shaped boss with the same shape as the LED, and a cylindrical protrusion extending beyond the boss. The combination of the boss and cylindrical protrusion allows for the mask to be over-etched, without significantly effecting the shape of the LED. Thus, any non-uniformities etching process do not decrease the luminance, nor uniformity, of the LEDs.

Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Abstract: The present invention provides light-emitting devices with improved quantum efficiency. The light emitting diode structure comprising: a p-doped layer, an n-doped layer; and a multiple quantum well structure sandwiched between the p-doped layer and n-doped layer, wherein the multiple quantum well structure comprising a quantum well disposed between n-doped barrier layers.

Abstract: A display apparatus includes a substrate including a display area and a sensor area, the display area including main pixels and the sensor area including auxiliary pixels and a transmission portion; a first pixel electrode and a first emission layer in each of the main pixels; a second pixel electrode and a second emission layer in each of the auxiliary pixels; an opposite electrode integrally arranged in the display area and the sensor area; and a metal layer at least partially surrounding the transmission portion, wherein the opposite electrode has an opening corresponding to the transmission portion.

Abstract: A semiconductor light emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, a first transparent electrode layer on the second conductivity-type semiconductor layer, a first insulating layer on the first transparent electrode layer, the first insulating layer including a plurality of through-holes, a reflective electrode layer on the first insulating layer and connected to the first transparent electrode layer through the plurality of through-holes, and a transparent protection layer covering upper and side surfaces of the reflective electrode layer, the transparent protection layer being on a portion of the first insulating layer.

Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.

Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.

Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures.

Abstract: Showerheads for independently delivering different, mutually-reactive process gases to a wafer processing space are provided. The showerheads include a first gas distributor that has multiple plenum structures that are separated from one another by a gap, as well as a second gas distributor positioned above the first gas distributor. Isolation gas from the second gas distributor may be flowed down onto the first gas distributor and through the gaps in between the plenum structures of the first gas distributor, thereby establishing an isolation gas curtain that prevents the process gases released from each plenum structure from parasitically depositing on the plenum structures that provide other gases.

Abstract: An ion-sensitive field effect transistor (ISFET) is provided that has enhanced sensitivity due to an increased passivation capacitance, Cp. The increased Cp is obtained by increasing the surface area of the passivation layer by forming particles (metallic, semiconductor or dielectric) in a micro-well, and by embedding the particles in an electrically conductive liner that is formed under the passivation layer and within the micro-well.

Abstract: A component-mounting resin substrate includes a resin substrate and a component. The resin substrate includes a thermoplastic resin body. The component is mounted on the resin substrate by ultrasonic bonding. In a mounting area of the resin body in which the component is mounted, a cavity that is hollowed from a mounting surface on which the component is mounted is defined. A plating layer that includes a material harder than the resin body is disposed on at least a portion of a wall surface of the cavity.

Abstract: Disclosed is a semiconductor device and method of manufacturing a semiconductor device that includes planarizing surfaces of a semiconductor substrate and a carrier substrate and then placing the semiconductor substrate on the carrier substrate such that the planarized surfaces of each are adjoining and allowing the semiconductor substrate to bond to the carrier substrate using a Van der Waals force. The method also includes forming a metal filled trench around the semiconductor substrate and in contact with the carrier substrate, which can also be formed of metal. The metal filled trench and carrier substrate together form a metal cage-like structure around the semiconductor substrate that can serve as a heat sink, integrated heat spreader, and Electro-Magnetic Interference shield for the semiconductor substrate.