Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a display region and a border region. The border region includes a first border and a second border arranged oppositely in a first direction. The display region includes a hollowed-out region, a second sub-display region and a primary display region, a data drive port located in the border region and data lines extended in the first direction. The data lines include second data lines located in the second sub-display region and auxiliary data lines located in the primary display region. The data drive port provides a data signal to sub-pixels in the second sub-display region through the auxiliary data lines and the second data lines.

Abstract: A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type semiconductor, supplying a second substrate, forming a radical oxide layer on the front face of the first substrate by executing a radical oxidation, assembling, by a step of direct bonding, the first substrate and the second substrate so as to form an assembly including the radical oxide layer intercalated between the first and second substrates, executing a heat treatment intended to reinforce the assembly interface, and making disappear, at least partially, the radical oxide layer.

Abstract: One embodiment relates to a light emitting device which is free from electrostatic discharge by using an electrostatic discharge suppressing pattern including a resin having particles conductive and dispersed therein, the light emitting device comprising: a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a first electrode connected with the first conductive semiconductor layer; a second electrode connected with the second conductive semiconductor layer; and an electrostatic discharge suppressing pattern, which is overlapped with the first electrode and the second electrode, and of which first particles are dispersed in the resin so as to cover a gap between the first electrode and the second electrode.

Abstract: A semiconductor module according to one embodiment includes a circuit substrate and first and second transistors for upper and lower arms of a power conversion circuit. The circuit substrate includes a substrate having first and second insulating parts and a conductive layer disposed therebetween, first and second input interconnection patterns coupled to the first and second input terminals, and an output interconnection pattern coupled to an output terminal. The first and second transistors are electrically coupled to the first and second input terminals through the first and second input interconnection patterns, respectively. The conductive layer has a first area situated opposite the first input interconnection pattern and a second area electrically coupled to the first area. The second area is electrically coupled to the second input interconnection pattern.

Abstract: Showerheads for independently delivering different, mutually-reactive process gases to a wafer processing space are provided. The showerheads include a first gas distributor that has multiple plenum structures that are separated from one another by a gap, as well as a second gas distributor positioned above the first gas distributor. Isolation gas from the second gas distributor may be flowed down onto the first gas distributor and through the gaps in between the plenum structures of the first gas distributor, thereby establishing an isolation gas curtain that prevents the process gases released from each plenum structure from parasitically depositing on the plenum structures that provide other gases.

Abstract: A semiconductor device includes: a first substrate having connectors at a first surface; a second substrate bonded with the first substrate having through-holes in a stacking direction of the first and second substrates for respectively exposing the connectors; through-electrodes respectively arranged at through-holes and electrically connected with the connectors; and a protective film for integrally covering the through-electrodes. Frame-shaped slits are formed to respectively surround the through-holes when viewed in a normal direction with respect to the first surface of the first substrate. The protective film is separated by the slit into a region inside the slit and a region outside the slit.

Abstract: According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.

Abstract: A circular printed memory device and a method for fabricating the circular printed memory device are disclosed. For example, the circular printed memory device includes a base substrate, a plurality of bottom electrodes arranged in a circular pattern on the base substrate, a ferroelectric layer on top of the plurality of bottom electrodes and a single top electrode on the ferroelectric layer that contacts each one of the plurality of bottom electrodes via the ferroelectric layer.

Abstract: A fan-out semiconductor package includes a core member having a through-hole. A semiconductor chip is in the through-hole and has an active surface with connection pads and an inactive surface opposing the active surface. An encapsulant encapsulates at least portions of the core member and the semiconductor chip and fills at least a portion of the through-hole. A connection member is on the core member and the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads. The core member includes a groove portion penetrating from a wall of the through-hole up to an outer side surface of the core member in a lower portion of the core member on which the connection member is disposed.

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

Abstract: Implementations of image sensors may include a silicon layer having a first side and a second side opposite the first side, an opening extending into the silicon layer from the first side of the silicon layer toward the second side, a via extending into the silicon layer from the second side of the silicon layer, and a conductive pad within the opening. The conductive pad may be coupled to the via. The opening may include a fill material. At least a portion of the fill material may form a plane that is substantially parallel with the first side of the silicon layer. The conductive pad may be exposed through an opening in the fill material.

Abstract: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.

Abstract: A capacitive micro electrical mechanical system (MEMS) pressure sensor in one embodiment includes a base layer, a lower oxide layer supported by the base layer, a contact layer extending within the lower oxide layer, a membrane layer positioned generally above the lower oxide layer, the membrane layer including at least one protrusion extending downwardly through a portion of the lower oxide layer and contacting the contact layer, a nitride layer extending partially over the membrane layer, an upper oxide layer above the nitride layer, a backplate layer directly supported by the membrane layer and positioned above the upper oxide layer, a front-side etched portion exposing a first portion of the membrane layer through the upper oxide layer and the nitride layer, and a backside etched portion extending through the base layer, the backside etched portion at least partially aligned with the front-side etched portion.

Abstract: An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

Abstract: The method for manufacturing an object comprises the steps of (a) providing a wafer comprising a multitude of semi-finished objects; (b) separating said wafer into parts referred to as sub-wafers, at least one of said sub-wafers comprising a plurality of said semi-finished objects; (c) processing at least a portion of said plurality of semi-finished objects by subjecting said at least one sub-wafer to at least one processing step; and preferably also the step of (d) separating said at least one sub-wafer into a plurality of parts.

Abstract: A method of forming a vertical transport fin field effect transistor (VT FinFET), including, forming a plurality of vertical fins on a substrate, forming a sacrificial liner on at least two of the plurality of vertical fins, forming sidewall spacers on the vertical surfaces of the sacrificial liner, wherein the sidewall spacers are on opposite sides of the at least two of the plurality of vertical fins, and removing a portion of the sacrificial liner to form an l-shaped channel adjacent to each of the at least two of the plurality of vertical fins.

Abstract: A display panel includes a plurality of light-emitting elements. Light emitted from a first light-emitting element has a CIE 1931 chromaticity coordinate x of greater than 0.680 and less than or equal to 0.720 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.260 and less than or equal to 0.320. Light emitted from a second light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.130 and less than or equal to 0.250 and a CIE 1931 chromaticity coordinate y of greater than 0.710 and less than or equal to 0.810. Light emitted from a third light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.120 and less than or equal to 0.170 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.020 and less than 0.060.

Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

Abstract: A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers of the plurality of second spacers and a first set of mandrel structures of the plurality of mandrel structures. A second set of second spacers of the plurality of spacers and a second set of mandrel structures of the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.