Patents Examined by Andrew Q. Tran
  • Pipeline-controlled semiconductor memory device with reduced power consumption and memory access time
    Patent number: 9053762
    Abstract: A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals, includes a first buffer circuit operating as a pipeline register. A second bus for bidirectional transfer of write/read data, includes a second buffer circuit operating as a pipeline register. A first control circuit sequentially sends the address/control signals on the first bus, and a second control circuit sequentially sends/receives write/read data on the second bus.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 9, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Atsunori Hirobe
  • Non-transitory computer-readable media describing a hybrid volatile and non-volatile memory device with an overlapping region of addressable range of storage cells
    Patent number: 9047942
    Abstract: Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: June 2, 2015
    Assignee: Rambus Inc.
    Inventor: Scott C. Best
  • Sense amplifier for static random access memory with a pair of complementary data lines isolated from a corresponding pair of complementary bit lines
    Patent number: 9047980
    Abstract: A sense amplifier for a static random access memory (SRAM) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an SRAM cell. A second pass gate transistor is driven by a bit line complement associated with the SRAM cell. A first pull down transistor is coupled to the first pass gate transistor and a second pull down transistor is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pull down transistor with the first pass gate transistor. A data line complement is coupled to a node coupling the second pull down transistor with the second pass gate transistor.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Pankaj Agarwal, Shiju K. Kandiyil, Krishnan S. Rengarajan
  • Memory controller and method of calibrating a memory controller
    Patent number: 9042188
    Abstract: A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: May 26, 2015
    Assignee: ARM Limited
    Inventors: Gyan Prakash, Nidhir Kumar
  • On chip dynamic read level scan and error detection for nonvolatile storage
    Patent number: 9036417
    Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 19, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Wenzhou Chen, Zhenming Zhou, Jun Wan, Deepanshu Dutta, Yi-Chieh Chen, Dana Lee
  • Method and apparatus for staggered start-up of a predefined, random or dynamic number of flash memory devices
    Patent number: 9036423
    Abstract: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: May 19, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Bradley Edman Sundahl, Sean Michael O'Mullan, Gregory Charles Yancey, Kenneth Alan Okin
  • Method and apparatus for testing memory utilizing a maximum width of a strobe signal and a data width of a data signal
    Patent number: 9036437
    Abstract: A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Wistron Corporation
    Inventor: Min-Hua Hsieh
  • Method of operating a nonvolatile memory by reprogramming failed cells using a reinforced program pulse in an idle state and memory system thereof
    Patent number: 9013934
    Abstract: A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Hyuk Lee
  • Semiconductor memory device capable of preventing degradation of memory cells and method for erasing the same
    Patent number: 9001586
    Abstract: A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Deung Kak Yoo
  • Method of overlapping interconnect signal lines for reducing capacitive coupling effects
    Patent number: 9001605
    Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventor: David V. Carlson
  • Static random access memory devices having read and write assist circuits therein that improve read and write reliability
    Patent number: 8995208
    Abstract: Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. The memory device further includes at least one bit line electrically coupled to the memory cell and a read assist circuit. The read assist circuit may be configured to improve read reliability by partially discharging the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jonghoon Jung, Sounghoon Sim
  • Coarse and fine programming in a solid state memory
    Patent number: 8995182
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Pre-charge during programming for 3D memory using gate-induced drain leakage
    Patent number: 8988937
    Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Dunga, Yingda Dong, Wendy Ou
  • Method of increasing a timing margin for relaying data to a memory array
    Patent number: 8988967
    Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: March 24, 2015
    Assignee: Nanya Technology Corp.
    Inventors: Phat Truong, Tien Dinh Le
  • Pre-charge during programming for 3D memory using gate-induced drain leakage
    Patent number: 8988939
    Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Dunga, Yingda Dong, Wendy Ou
  • Method and device for writing block data to an embedded DRAM free of address conflicts
    Patent number: 8988951
    Abstract: Embodiments of the present invention provide a method and a device for writing data. The method includes: receiving a data block that is to be written in an EDRAM; obtaining, according to a status of a bank in the EDRAM, usable addresses corresponding to usable banks in the EDRAM; selecting an address from the usable addresses as a write-in address of the data block; and writing the data block in a bank corresponding to the write-in address. In the embodiments of the present invention, problems in the prior art that a conflict occurs when a data block is written in a bank and a conflict occurs when a data block is read from a bank can be avoided, and working efficiency of the EDRAM is improved.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 24, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xian Li, Hongbo Shi, Yalin Bao
  • Non-volatile memory capable of programming cells by hot carrier injection based on a threshold voltage of a control cell
    Patent number: 8976581
    Abstract: A non-volatile memory system includes a bit line and a plurality of memory cells associated with the bit line and coupled in a serial manner. The system further has a control circuitry in communication with the memory cells, wherein the control circuitry programs a target cell selected from the memory cells by applying a bit line voltage on the bit line in order to promote hot carrier injection into the target cell. The circuit also applies a programming voltage on the target cell under a hot carrier injection mechanism. Moreover, the circuit also applies a control voltage on a control cell, which is adjacent to the target cell when programming the target cell, wherein the control voltage is dependent on the threshold voltage of the control cell and the control voltage is less than the programming voltage.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: March 10, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Wen Jer Tsai, Ping Hung Tsai
  • Method and devices for memory cell erasure with a programming monitor of reference cells
    Patent number: 8971121
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Andrei Mihnea
  • Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor
    Patent number: 8964463
    Abstract: A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: February 24, 2015
    Assignee: Genusion, Inc.
    Inventors: Natsuo Ajika, Taku Ogura, Masaaki Mihara
  • Semiconductor memory device capable of optimizing an operation time of a boosting circuit during a writing period
    Patent number: 8964489
    Abstract: When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito