Patents Examined by Andrew Q. Tran
  • Circuit that selects EPROMs individually and in parallel
    Patent number: 9592664
    Abstract: An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: March 14, 2017
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Paul I. Mikulan, Bee Ling Peh
  • Semiconductor memory device having unequal pitch vertical channel transistors employed as selection transistors and method for programming the same
    Patent number: 9595568
    Abstract: A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate. The transistor bodies may have an unequal pitch and a common height. Some of the transistor bodies can be misaligned with the vertical bit lines to fit the transistors to the stack. A method for programming the three-dimensional memory structure includes forming one or two channels in a transistor body to provide a current to selected memory cells. Programming can initially use one channel and subsequently use two channels based on a programming progress. A method for fabricating a semiconductor device includes etching a gate conductor material so that shared and non-shared control gates have a common height.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: March 14, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Teruyuki Mine
  • Variable resistance memory device and verify method thereof
    Patent number: 9595327
    Abstract: A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kikuko Sugimae, Reika Ichihara
  • Input circuit of three-dimensional semiconductor apparatus capable of enabling testing and direct access
    Patent number: 9589670
    Abstract: An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. The input circuit of the semiconductor apparatus may include a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal, and a storage unit configured to store the comparison signal.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 7, 2017
    Assignee: SK hynix Inc.
    Inventor: Dae Suk Kim
  • Sensing scheme for high speed memory circuits with single ended sensing
    Patent number: 9583208
    Abstract: A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a first bit value (for example, bit value 1.) If the bitline voltage stays below a low threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a second bit value (for example, bit value 0).
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: February 28, 2017
    Assignee: Synopsys, Inc.
    Inventors: Sachin Taneja, Vaibhav Verma, Pritender Singh, Sanjeev Kumar Jain
  • Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value
    Patent number: 9576655
    Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: February 21, 2017
    Assignee: HGST NETHERLANDS B.V.
    Inventors: Evangelos S. Eleftheriou, Angeliki Pantazi, Nikolaos Papandreou, Haris Pozidis, Abu Sebastian
  • Read measurement of a plurality of resistive memory cells for alleviating resistance and current drift
    Patent number: 9576650
    Abstract: A method for read measurement of a plurality N of resistive memory cells having a plurality M of programmable levels is suggested. The method includes a step of reading back from a number of reference cells to obtain a reading back parameter, a step of determining an actual read voltage for the N memory cells based on the obtained reading back parameter for obtaining a target read current at a following read measurement, and, a step of applying the determined actual read voltage to the N memory cells at the following read measurement.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abu Sebastian, Nikolaos Papandreou, Charalampos Pozidis
  • Conditioning phase change memory cells
    Patent number: 9558817
    Abstract: A method for conditioning at least one Phase Change Memory, PCM, cell. The PCM cell is characterized by a number of pre-defined characteristics or properties. For pre-conditioning, at least one conditioning pulse is applied to the PCM such that at least one selected characteristic of the number of pre-defined characteristics is changed to a desired value.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Charalampos Pozidis
  • Semiconductor memory with a multi-layer passivation layer formed over sidewalls of a variable resistance element
    Patent number: 9559298
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes a variable resistance element formed over a substrate, and a multi-layer passivation layer positioned over sidewalls of the variable resistance element and having two or more insulating layers formed over the sidewalls of the variable resistance element.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: January 31, 2017
    Assignee: SK hynix Inc.
    Inventor: Ga-Young Ha
  • Resistive semiconductor memory capable of performing incremental step pulse programming (ISPP) based on digital code values of memory cells
    Patent number: 9548114
    Abstract: Disclosed are a semiconductor memory apparatus, a program method, and a program system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells and a control block configured to variably control, based on digital code values reflecting resistance states of the resistive memory cells, at least one of a initial voltage magnitude and an initial voltage applying time in an incremental step pulse programming (ISPP) mode for the plurality of memory cells. Therefore, even in the case of the worst cell, the incremental step of the ISPP may be minimized, and the writing time may be reduced, limiting unnecessary current consumption.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: January 17, 2017
    Assignee: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Keewon Kwon, Jongmin Baek, Dongjin Seo
  • Semiconductor device with a sense amplifier unit responsive to a voltage change of input signals and a sense control signal
    Patent number: 9536576
    Abstract: A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate an output signal in response to the sense voltage and the input signals.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 3, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hyung Soo Kim
  • Apparatus and method for reading a storage device with a ring oscillator and a time-to-digital circuit
    Patent number: 9514812
    Abstract: According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit. The method for storage device reading may further include determining a value of data stored in the storage device based on the measurement.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 6, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Robert J. Brooks
  • Stack bank type semiconductor memory apparatus capable of improving alignment margin
    Patent number: 9502078
    Abstract: A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: November 22, 2016
    Assignee: SK HYNIX INC.
    Inventors: Seung Wook Kwak, Sang Hoon Shin, Keun Soo Song
  • Writing multiple levels in a phase change memory
    Patent number: 9502107
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack R. Morrish
  • Auto-suspend and auto-resume operations for a multi-die NAND memory device to reduce peak power consumption
    Patent number: 9443600
    Abstract: A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Ali Ghalam, Dean Nobunaga, Jason Guo
  • Identification of a condition of a sector of memory cells in a non-volatile memory
    Patent number: 9443566
    Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: September 13, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marcella Carissimi, Marco Pasotti, Fabio De Santis
  • Programming method of memory array
    Patent number: 9437303
    Abstract: A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chu-Yung Liu, Hsing-Wen Chang, Yao-Wen Chang, Tao-Cheng Lu
  • Memory operation latency control
    Patent number: 9437264
    Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Han-Sung Chen, Ming-Chao Lin
  • Integrated setback read with reduced snapback disturb
    Patent number: 9437293
    Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Arjun Kripanidhi, Kiran Pangal, Lark-Hoon Leem, Balaji Srinivasan
  • Stack bank type semiconductor memory apparatus capable of improving alignment margin
    Patent number: 9437252
    Abstract: A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: September 6, 2016
    Assignee: SK hynix Inc.
    Inventors: Seung Wook Kwak, Sang Hoon Shin, Keun Soo Song