Abstract: A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal.

Abstract: A semiconductor integrated circuit adaptable to any logic circuits using a common mask with the exception of a mask of metallic wirings so as to drastically improve performance of custom LSIs. The semiconductor integrated circuit comprises a logic circuit having a plurality of input terminals and at least one output terminal. The logic circuit includes a plurality of circuit blocks of the same circuit construction. Each of the circuit blocks has at least two stages of inverter formed by MOS semiconductor devices and at least one layer of a wiring pattern having a different pattern. The output signal of each block is defined by a predetermined function of an input signal.

Abstract: A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired.

Abstract: An evaluation tree circuit is disclosed that produces a generate, a propagate, and a zero output for use in carry lookahead adders. Another evaluation tree circuit is disclosed that merges the generate, propagate, and zero signals from several adjacent bits or groups of bits. These evaluation trees may be used in self-resetting CMOS or CVSL circuits. They can be used to reduce the number of levels of logic in a carry lookahead adder. They can also be used to form a magnitude comparator, which is also disclosed.

Abstract: An output buffer circuit for a memory device comprising a pull-up path including first and second PMOS transistors for forming two parallel charging paths, and a pull-down path including first and second NMOS transistors for forming two parallel discharging paths. The first and second PMOS transistors are selectively operated according to a level of an output voltage at an output terminal to perform a charging operation for a load capacitance connected to the output terminal. The first and second NMOS transistors are selectively operated according to the level of the output voltage at the output terminal to perform a discharging operation for the load capacitance through a lead inductance.

Abstract: The integrated circuit includes a plurality of row decoder-driver circuits, each for raising the voltage of a respective row line. Each of the plurality of row decoder-driver circuits includes an address decoder capable of receiving a plurality of address bits. The plurality of address bits, when decoded, identify one of the plurality of row decoder-drivers to provide an output. Each of the plurality of row decoder-drivers has an input transistor having a gate. The input transistor has a conduction path coupled between a power supply node and the address decoder. A signal generating circuit receives a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit. The signal generating circuit provides an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits.

Abstract: The parallel antifuse scheme may be applied to a field programmable gate array architecture (10) having a logic module (16) with an output coupled to an output track (34, 54, 114, 144, 178, 198) coupled via a cross antifuse (38, 58, 116, 184, 208) to an connecting track (36, 56, 64, 118, 154, 182, 205, 206). The connecting track is further coupled via at least one cross antifuse (44, 46, 72, 74, 120, 122, 160, 162, 190, 218, 220) to at least one input track (40, 42, 68, 70, 188, 214, 216) coupled to an input of at least one logic module. The circuit includes a compensation track (124, 150, 180, 200) running generally in parallel with the output track and at least one parallel antifuse (125, 158, 186, 212) programmably coupling the compensation track (124, 150, 180, 200) and the connecting track. One or more controllable switch (130, 152, 174, 176, 194, 196), such as a pass transistor, is coupled between the output track and the compensation track.

Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: A current transition rate control circuit is provided, comprising first and second data inputs; first and second charge/discharge circuits for receiving the first and second data inputs; a first reference voltage circuit for sending a first control signal and a second reference voltage circuit for sending a second control signal to, respectively, the first and second charge/discharge circuits; and first and second output transistors coupled, respectively, to the outputs of the first and second charge/discharge circuits. The circuit controls the switching speed of the output transistors to minimize current spikes on the output. The circuit may include a pre-driver circuit for (i) receiving a single data input and outputting the first and second data inputs, and (ii) receiving a circuit disabling signal and placing the circuit in a high impedance state which turns off both of the output transistors.

Abstract: A terminated driver circuit 10 having a controlled output impedance includes an external impedance 12 connected to a bias generator circuit 20 which is operable to generate a plurality of bias voltages in response to a reference current generated by bias generator circuit 20 wherein the reference current magnitude is a function of external impedance 12. An output driver circuit 30 is connected to bias generator circuit 20. Output driver circuit 30 has a plurality of output devices connected to a transmission line and is operable to receive the plurality of bias voltages from bias generator circuit 20 and multiplex them such that only a single bias voltage is driving a single output device at a time. The plurality of bias voltages causes the plurality of output devices to have specific, controlled impedances when conducting wherein the controlled output impedances match the characteristic impedance of a transmission line 40 being driven by terminated driver circuit 10 thereby reducing waveform reflections.

Abstract: An improved sample and hold circuit utilizing a buffer circuit to reduce the effective resistance of the switches used to couple an input signal to storage capacitors. The effective resistance of the switches are reduced by placing the switches within the feedback path of the buffer. The buffer may be shared among multiple sample and hold circuits.

Abstract: A level shifter circuit for converting an input signal referenced to the least positive power supply (typically ground) to an output signal referenced to a higher, more usable voltage. The level shifter circuit generally includes a current mirror arrangement for coupling first and second current legs. The first current leg includes an NPN bipolar transistor arranged in series with a resistor R and a PNP bipolar transistor, wherein the NPN and PNP transistors have base inputs V.sub.ref and V.sub.in, respectively. The second current leg comprises a series arrangement of a diode-connected NPN bipolar transistor, a resistor R and a diode-connected NPN bipolar transistor. An output voltage (V.sub.OUT =V.sub.ref -V.sub.in), is taken at the collector of the diode-connected NPN transistor in the second current leg.

Abstract: A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a pre-charge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.

Abstract: Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers.

Abstract: Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers.

Abstract: A bus interface logic integrated circuit having a function of bus interfacing a system bus with a higher-order module, including a programmable chip connected between the system bus and the higher-order module and adapted to bus interface the system bus and the higher-order module with each other, the programmable chip initiating transmission and receipt of data under a control of the higher-order module.

Abstract: An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.

Abstract: A bidirectional tristate buffer includes a default input such that the signal applied to one of the lines connected to the bidirectional buffer is always applied to the input terminal of a buffer element in the bidirectional buffer and applied by the output terminal of the buffer element to any load which may be driven by the buffer output terminal. In a preferred embodiment, the tristate bidirectional buffer with default input requires only four transistors plus the transistors which comprise the buffer element and memory cells for controlling the direction.

Abstract: A method and structure for controlling ground bounce and power supply noise during switching is provided in which a plurality of pull-up and/or pull-down transistors are provided whose turn on during switching is controlled in order to provide the desired slew rate in order to control the deleterious effects of ground bounce and power supply noise. In one embodiment, a plurality of pass transistors are used in order to delay a logical signal in order to control the slew rate. In one embodiment, these pass transistors are sensitive to ground bounce, providing a positive feedback mechanism to further enhance the control of ground bounce. In one embodiment, an RC network is conveniently formed in order to control slew rate, and in one embodiment the RC network is sensitive to ground bounce, providing positive feedback in order to further control the slew rate as a result of detected ground bounce.

Abstract: A method and circuitry for providing dual row selection using a multiplexed tri-level decoder is disclosed. For one embodiment, the multiplexed tri-level decoder is a 3:8 decoder, the major components of which are a buffer and 8 three input NAND circuits. The NAND circuits are peculiar in that the inputs are referenced to a VCC operational voltage supply, and the outputs are referenced to a VPX tri-level supply voltage. The output of each NAND circuit is used to select one row or word line. During preconditioning and post conditioning, the decoder is required to enable two adjacent rows: the row selected and the next row. The present design implements dual row selection by adding a pass transistor that connects the word line enable driver to the driver of the previous row within the VPX level circuitry. This is in contrast to the previous design approach of implementing dual row selection by using VCC level logic. The disclosed implementation eliminates gates in the speed path of the circuit.