Abstract: A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor.

Abstract: A conventional CMOS inverter circuit is operated in a low-power-dissipation mode by being connected to a pulsed power supply. The circuit is utilized as a basic building block to realize a variety of logic and memory functions.

Abstract: According to the present invention, a plurality of programmable multi-bit output functional block modules, each capable of assuming the functionality of one of the set of adders, subtracters, magnitude comparators, identity comparators, up/down counters, registers, multi-bit ANDs, and similar devices, are placed in predetermined locations of the FPGA chip. The number of functional blocks is much fewer than the number of FPGA modules on the chip. Each of the functional blocks has a plurality of inputs and outputs, each of which is capable of being connected to the neighboring programmable interconnect resources. Communication between and amongst functional blocks is carried out with the standard programmable resources available on board the FPGA chip.

Abstract: A trimming circuit has a plurality of zener zap diodes, a group of switching devices for selectively zapping the zener zap diodes, and a decoder circuit for controlling the ON/OFF states of the switching devices.

Abstract: A device includes an electrically programmable semiconductor integrated circuit or circuits, such as a Field Programmable Gate Array. Each circuit comprises a plurality of fundamental sections connected to a plurality of signal lines, wherein each fundamental section is permitted to carry out both operation in a logical operation mode for performing a logical operation using signals delivered from the signal lines and operation in a wiring formation mode for carrying out setting of connecting states between the respective signal lines, whereby the semiconductor integrated circuit is operable in any operation mode arbitrarily selected. The fundamental section may be of a structure capable of performing a sequential logical operation as the logical operation mode. In this case, at least one of the memories of the memory section corresponds to a latch memory.

Abstract: A variable drive strength buffer circuit is provided that automatically adjusts its associated drive strength to compensate for variations in manufacturing parameters, environmental conditions and operating conditions. As a result, electromagnetic interference, power supply noise, edge rates and ringing may be reduced. The self-adjusting variable drive buffer circuit may be fabricated on an integrated circuit and includes a speed detector unit that measures the relative speed of the integrated circuit. In one embodiment, a self-adjusting variable drive strength buffer circuit includes a circuit speed detector unit having a delay chain consisting of a plurality of variable delay elements. When the delay chain length is matched to the period of an input clock, the length of the chain is an accurate measure of the relative "speed" of the transistors making up the delay chain and therefore of the other transistors on the integrated circuit chip.

Abstract: An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry.

Abstract: A level shifting circuit for converting a lower logic level into a higher logic level is arranged to prevent a large through current from flowing when the level of an input signal varies. A latch circuit for latching an input binary signal comprises first and second transistors to which there are connected in series third and fourth transistors, respectively, for blocking a current during the level shifting period. Fifth and sixth transistors having a small current capacity are connected parallel to the set of first and third transistors and the set of second and fourth transistors, respectively, to quickly respond to a level change. The fifth and sixth transistors may be dispensed with.

Abstract: A neuron element with electrically programmable synaptic weight for an artificial neural network features an excitatory-connection floating-gate transistor and an inhibitory-connection floating-gate transistor. The control gate electrodes of the two transistors are connected together, and the drain electrode of the inhibitory-connection transistor is connected to the source electrode of the excitatory-connection transistor. Both of the excitatory-connection and inhibitory-connection transistors have programming electrodes. The control gate electrodes and the programming electrodes can be utilized to program the threshold voltages of the transistors and thus the synaptic weight of the neuron element.

Abstract: A logic circuit having a programmable first logic circuit stage and a fixed or dedicated combinatorial second logic circuit stage, serving as a macrocell for the first logic circuit stage. At least one input to the logic circuit is connected directly to the second stage, bypassing the first stage. The first stage may be a programmable logic device with a programmable AND plane followed by an OR plane, and is functionally flexible. The second stage has at least two groups of CMOS logic gates arranged in sequence and connected in a fixed manner by hardwiring so as to implement a specified combinatorial logic function that is representable in sum-of-products form, and is fast compared to the first stage. The outputs from the first stage control logic operations of the second stage upon the directly connected input or inputs.

Abstract: The design and implementation of a low power CMOS bi-directional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The buffer further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels. An multivoltage I/O buffer having multiple input-receiving NOR gates is also described. The NOR gates of the multivoltage I/O buffer having triggering levels optimized for differing core voltage levels. Also described is a host adapted system for interfacing between and removable peripheral card and a host computer. The host adaptor includes an integrated circuit employing the multivoltage bi-directional I/O buffer.

Abstract: An output buffer circuit for limiting ground bounce or output signal ringing. The output buffer utilizes two pull down transistors connected to two separate grounds as well as two pull up transistors connected to two separate V.sub.DD power supplies. When the buffer output is switched from high to low, a one shot switching means is provided for switching on a first pull down transistor connected to a noisy ground for a short time delay period allowing ground bounce to occur on the noisy ground, and then switching on the second pull down transistor connected to a quiet ground while switching the first pull down transistor off. Similarly, the one shot switching means switches between the two pull up transistors to limit output signal ringing on a quiet V.sub.DD power supply. The buffer circuit further includes a lead frame with separate noisy and quiet ground leads terminating in a single pin, with the noisy and quiet ground leads overlying a floating conductive plane to reduce mutual inductance.

Abstract: A basic logic circuit 10 which functions as a data selector consists of a basic circuit 11, a HET (hot electron transistor) 12, the first and second emitters of which are connected to the first emitter of a HET 16 and a data input end A respectively, and an inverter 13 connected to an output end of the circuit 11. In a HET 14 having no base electrode, its collector is connected to a power supply line VCC via a load resistor 15, its first emitter is used exclusively for current output by connecting to the collector of the HET 16 the second emitter of which is connected to a power supply line VSS, its second emitter is used for current input/output by directly connected to a control input end S, and its third emitter is used exclusively for current input by connecting to the first emitter of a HET 17 the second emitter of which is connected to a data input end B. An output data Q is equal to an input data A/B when a control data S is high/low level respectively.

Abstract: A 3-state buffer circuit applicable for a CMOS output drive circuit is disclosed. The output circuit provides reduced ground noise and delay time of an output signal by decreasing a counter-electromotive force generated upon turning ON of the output transistor. The circuit includes a subsidiary drive circuit for applying a voltage less than the power source Vcc to a gate of an NMOS transistor connected on the ground side of the drive circuit so that generation of the counter-electromotive force is minimized.

Abstract: An automatic SCSI termination circuit has means detecting the occupied or vacant status of one or more SCSI interconnection ports and enables or disables termination, which is applied to the ports without need for manual intervention.

Abstract: A switching circuit for an FET transistor includes a controlled current circuit coupled to the gate of the FET. The input to the controlled current circuit represents a desired rate of change of gate voltage of the FET and is generated by a circuit responsive to the average specific transconductance of two FETs of similar specific transconductance operating at different drain circuit densities.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: A emitter coupled logic circuit is reduced in circuit scale, while maintaining the speed of shift registers and compatibility with analog circuits. When data held in the first self-holding circuit section 41 or the second self-holding section 42 is deleted, the threshold voltage VTH applied to the base electrodes of the first and third transistors Q41 and Q43 is set outside the logical amplitude. When data is transferred, also, the threshold voltage VTH is set at a value intermediate to the logical amplitude. Because of this the data held in the first and second self-holding circuit sections can be reliably deleted without an increase in the number of elements.

Abstract: A BiCMOS non-inverting buffer circuit (40) with small fan-in capacitance and excellent bipolar output drive. The circuit is ideal for buffering CMOS logic gates from excessive fan-out loads. The circuit also is less complex and more silicon efficient than present buffer circuit implementations, it provides improved transient saturation charge clamping and one buffer macro in an ASIC library can provide extended drive capability to all CMOS logic gates in the library.

Abstract: A structure for and method of operating a transition-controlled off-chip driver is disclosed. Turn-on of output pulling devices is controlled, while turn-off is uncontrolled. An AC voltage reference circuit dissipating essentially zero DC power provides a reference voltage for control during transition. Turn-on control dissipates during transition, and ends when transition is complete without the use of output feedback.