Abstract: The logic circuit of the level shifting circuit of a high side MOS gate device is made reset dominant to make the circuit immune to noise glitches. The reset dominance is obtained by causing a reset signal to be produced at a wider range of high side floating supply offset voltage than that at which the set signal can be produced to prevent the chance of a set when the high side power MOSFET should be off. The reset dominance is obtained by increasing the size of the reset voltage dropping resistor or by adjusting the input threshold of the circuit reading the set and reset voltage dropping resistors.

Abstract: The data input/output circuit for full duplex communication includes a data accepting and sending circuit which has an input/output terminal connected to a processor provided within a digital apparatus, and which receives data from the processor, transmits the data and receives outside data through the input/output terminal, a reference circuit which divides a voltage level of the data transmitted from the data accepting and sending circuit and produces a divided voltage level, a differential receiving circuit which has one input terminal connected to the input/output terminal and another input terminal connected to the reference circuit, and which is not operated by a zero voltage difference between the input terminals when the data is transmitted from the input/output terminal but operated by a voltage difference between the input terminals when the data is received through the input/output terminal, the data being supplied to the processor of the digital apparatus, a reference circuit for generating an out

Abstract: In the case where an external signal line is driven by a circuit other than an output circuit with a voltage higher than an on-chip power-source voltage, if an output transistor is activated in the output state immediately after the driving of the external signal line by the above other circuit was cancelled, a voltage equal to or higher than the breakdown voltage of an oxide film of a transistor composing the output circuit is applied thereto. To prevent this, there is provided a voltage detecting means for detecting a voltage value of the above external signal line being higher than a value in the vicinity of the internal power-source voltage and generating a detection signal, which inhibits the activation of the output transistor.

Abstract: A bootstrap circuit comprising an inverter for inverting an input signal from an input node, a delay stage for delaying the input signal from the input node for a predetermined time period, a first capacitor connected between an output terminal of the inverter and a junction node, a first NMOS transistor for transferring the input signal delayed by the delay stage to the junction node, the first NMOS transistor having a drain connected to an output terminal of the delay stage, a source connected to the junction node and a gate connected to a supply voltage source, a second capacitor connected between an output node and a ground voltage source, and a second NMOS transistor for transferring the input signal inverted by the inverter to the second capacitor connected to the output node in response to a signal charged on the first capacitor. According to the present invention, the bootstrap circuit bootstraps the input signal to a high voltage level at a high speed.

Abstract: Output characteristics of CMOS chips are controlled by providing a known and stable current to a representative transistor of known relative size in the CMOS chip, and arranging the output CMOS driving transistor(s) of the chip, which are of known size relative to the representative transistor, in current mirror relationship with the representative transistor. Two primary embodiments of the invention are provided. In a first primary embodiment (I.sub.d,SAT stabilization), the representative transistor is a diode-connected transistor with a saturation current which is generated by the current source and which is also provided to drive the output transistor device(s) when it is ON. In the second primary embodiment (R.sub.ON stabilization), instead of being diode-connected, a servo is used to adjust the gate voltage of the representative device until it is greater than the drain voltage by a desired amount. In this manner, the resistance (R.sub.

Abstract: An integrated circuit includes a bipolar logic stage and a CMOS logic stage. The bipolar logic stage includes a common emitter line positioned along a central axis, and a set of bipolar signal drive blocks arranged along the central axis. Each of the bipolar signal drive blocks includes a bipolar transistor with an emitter connected to the common emitter line. Each of the bipolar signal drive blocks further includes an emitter-base reverse voltage protection device. The CMOS logic stage includes a plurality of CMOS logic blocks connected to the set of bipolar signal drive blocks. The CMOS logic blocks are arranged in a compact configuration that is substantially perpendicular to the central axis. The CMOS logic stage performs logical operations on a set of input signals to generate a set of intermediate signals that are driven by the set of bipolar signal drive blocks onto the common emitter line.

Abstract: An 8-input, 1-output mux-based logic module for an FPGA is disclosed. The logic module comprises five separate multiplexers connected differently in the various embodiments of the present invention. The 8-input logic module can realize a total of 2390 unique functions. A 7-input, 1-output variation of the logic module of the preferred embodiment is also disclosed.

Abstract: A series-gated ECL driver, such as a series-gated ECL cut-off driver, is provided with settable output rise time and settable output fall time, in order to reduce noise at the output of the driver while limiting the delay resulting from such noise reduction. A method is also provided for so controlling an ECL driver. The driver includes at least two current switches fed by a current source. Each current switch includes a NOR side including one or more transistors, and an OR side including one or more transistors. The input to the NOR side of one such current switch can be buffered with an input emitter follower, and the output from that current switch can be buffered with an output emitter follower. A capacitance is connected across the one current switch and the current source, that is between the collector(s) and emitter(s) of the NOR side transistor(s) of that current switch, and the input side of the current source.

Abstract: A digital dynamic circuit is presented which effectively extends the percentage of each clock cycle available for logical operations. The circuit uses a two-phase overlapping clocking design which results in the circuit (1) having only a single latch delay, (2) being insensitive to mid-cycle clock jitter, and (3) being insensitive to the discrete nature of gate delays. Thus, the circuit can better utilize the time available to perform logic.

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10, 12, 14 with all such N-channel transistors coupled in series. A plurality of P-channel transistors 16, 18 coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Specifically, the gates of two of the N-channel transistors 12, 14 are connected by polysilicon lead 28 to the gate of transistor 16. This configuration forms a circuit primitive which is well adapted for use as a base cell in a programmable array device.

Abstract: An output buffer circuit for supplying a current to an output pad of an integrated circuit comprises an output driver circuit and a feedback circuit. The output driver circuit includes a first current supply element for supplying a small current to the output pad in response to an input logic signal. The feedback circuit includes a second current supply element for supplying a large current to the output pad and a circuit for generating a feedback voltage to control the second current supply element. The feedback voltage is responsive to the input logic signal and inversely follows the output pad voltage when the output pad voltage crosses a threshold. The output buffer provides excellent short circuit protection.

Abstract: In a ready signal control apparatus, connected between a CPU and a plurality of peripheral circuits, a ready signal generated from one of the peripheral circuits is transmitted to the CPU for only a certain definite time period after a selection signal is generated from the CPU.

Abstract: An integrated semiconductor circuit configuration includes one input of the circuit configuration for receiving a ternary input signal, and two outputs of the circuit configuration for supplying two binary output signals converted from the input signal. First, second, third and fourth resistors are connected in series between an operating voltage potential and a reference potential, defining a first connecting node between the first and the second resistors, a second connecting node between the second and the third resistors, and a third connecting node between the third and the fourth resistors. The second connecting node forms the input of the circuit configuration. A first threshold value decision circuit has an input connected to the first connecting node and has an output. A second threshold value decision circuit has an input connected to the third connecting node and has an output.

Abstract: A programmable logic device includes a plurality of logic cells in which logic functions are performed, a plurality of input lines for supplying signals to be processed by the logic cells, a plurality of output lines for receiving signals that have been processed by the logic cells, and a plurality of repeater circuits combining bipolar and CMOS transistor technologies for transferring data from one point in the PLD to another point. Unidirectional repeater circuits transfer data from a first data bus in the PLD to a second data bus in the PLD. Bidirectional repeater circuits maintain signal integrity by transferring data along the length of a single PLD data bus. The bipolar technology in the repeater circuits provides superior speed in data transfer, while the CMOS technology limits power consumption of the repeater circuits.

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Abstract: A pulsed static CMOS circuit. Improved static CMOS circuit speed is achieved without using a clock scheme like that in dynamic CMOS circuits. The disclosed circuit family is a pulsed static CMOS circuit which makes only a single transition during evaluation. The circuit is reset to a predetermined state by an input pattern, which is in favor of the faster switching direction of the static CMOS.

Abstract: A method and circuit for selectively or programmably controlling the polarity of a signal includes a two transistor invertor with its sources coupled to a select signal and its complement and its drains coupled to buffer circuits that pull the drains to full CMOS voltage rail levels. The circuit consumes no standby current and is fully restoring.

Abstract: A non-overlap signal generation circuit for a semiconductor memory device which generates two non-overlapped output signals of complementary logic levels with respect to one input signal. The circuit comprises first and second data paths. The first data path includes a first transistor for transiting a first output node from logic "0" to logic "1" when the input signal is transited from logic "0" to logic "1", whereas from logic "1" to logic "0" when the input signal is transited from logic "1" to logic "0", a first inverter for inverting the input signal, and a second transistor for transiting the first output node from logic "1" to logic "0" in response to an output signal from the first inverter.

Abstract: A transistor circuit apparatus comprises a MOS transistor to be improved, for preventing an avalanche breakdown, the MOS transistor being connected in a channel conductor path provided between one of power supply terminals and a terminal of an output, a separate circuit connected to the output terminal and driven by a voltage from a separate power supply, and a pull-down unit including a second transistor connected between one of said power supply terminals and a back gate of the MOS transistor, the second transistor being turned on with an output node of the separate circuit used as power supply when the MOS transistor remains at a ground potential level with no power supply potential supplied, thereby pulling down the potential level of a back gate node of the MOS transistor to the level of one of the power supply terminals.

Abstract: A logic module for use in gate arrays and the like includes five two input multiplexers 50, 52, 54, 56, 58. The module includes 10 data input terminals I1, I2, I3, I4, I5, I6, I7, I8, I9, I10. The first input terminals I1, I2 are connected to the data input terminals of multiplexer 50. Inputs I3, I4 and I5 are connected respectively to the select, the first data and second data inputs to multiplexer 52. Inputs I6, I7 are connected to the data inputs of multiplexer 54. Inputs I8, I9, I10 are connected to the first data, second data and select inputs to multiplexer 56. The output of multiplexer 52 is connected to the select input to multiplexers 50 and 54. The output of multiplexer 56 is connected to the select input to multiplexer 58 while the outputs of multiplexers 50 and 54 are respectively connected to the first and second data input to multiplexer 58. The output of multiplexer 58 comprises the logic circuit output O.