Patents Examined by Anthony Dinkins
  • Patent number: 6909596
    Abstract: A capacitor element includes a valve metal foil including a core layer and a porous layer on the core layer, a dielectric layer on a portion of the valve metal foil excluding an end portion of the valve metal foil, a solid electrolyte layer on the dielectric layer, a collector layer on the solid electrolyte layer, and a zinc layer on the end portion of the valve metal foil. A solid electrolytic capacitor includes the capacitor element, an insulating case for sealing the capacitor element as to expose the zinc layer, a nickel layer on the zinc layer, and an electrode provided on the case and electrically connected to the collector layer. The solid electrolytic capacitor has a small impedance even at high frequencies, and has a small overall size and a large capacitance.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: June 21, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Shimoyama, Yuji Mido
  • Patent number: 6909592
    Abstract: The present invention is directed to a method for fabricating a thin film capacitor of a metal/insulator/metal (MIM) structure, which is capable of enabling small-sizing of a semiconductor device while maintaining electrostatic capacity of a capacitor. The method comprises the steps of: forming a heterogeneous film on a lower insulation film on a structure of a semiconductor substrate; forming a plurality of projections by selectively etching the heterogeneous film; and forming a first electrode layer, a dielectric layer, and a second electrode layer on the lower insulation including the plurality of projections in order along a surface shape of the projections such that a plurality of projecting parts are formed in the first electrode layer, the dielectric layer and the second electrode layer, respectively.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: June 21, 2005
    Assignee: Dongbuanam Semiconductor Inc.
    Inventor: Young-Hun Seo
  • Patent number: 6906262
    Abstract: In a flexible print circuit having a plurality of signal wires, core wires formed from a shape memory material are provided on the two end portions thereof in the direction of width, and are caused to memorize a wiring completion shape within an electronic instrument in advance. In a wire harness having a plurality of signal wires, core wires formed from a shape memory alloy are disposed on the two sides of the planar signal wire array, or positioned along the central axis of the signal wires which are bundled into circular form. A guide frame for guiding a wire harness having a plurality of signal wires and which is caused to memorize in advance a shape which removes the wire harness from the movement range of a movable component within the electronic instrument.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: June 14, 2005
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Yuichi Fujimura
  • Patent number: 6906905
    Abstract: A three-dimensional micro electro-mechanical (MEMS) variable capacitor is described wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate are independently actuated. These electrodes are formed in an interdigitated fashion to maximize the capacitance of the device. The electrodes are jointly or individually actuated. A separate actuation electrode and a ground plane electrode actuate the movable electrodes. The voltage potential between the two electrodes provides a primary mode of operation of the device. The variation of the sidewall overlap area between the interdigitated fingers provides the expected capacitance tuning of the device. The interdigitated electrodes can also be attached on both ends to form fixed-fixed beams. The stiffness of the electrodes is reduced by utilizing thin support structures at the ends of the electrodes. The three dimensional aspect of the device avails large surface area.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventor: Anil K. Chinthakindi
  • Patent number: 6906908
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which covers the capacitor and has a first hole and a second hole, the first hole being provided apart from the capacitor and extending in a vertical direction with respect to a main surface of the semiconductor substrate, the second hole reaching an electrode of the capacitor, extending in the vertical direction with respect to the main surface of the semiconductor substrate and being shallower than the first hole, a tungsten plug provided in the first hole, a first oxygen barrier film provided between the tungsten plug and a side wall of the first hole, and a conductive plug provided in the second hole and connected to the electrode of the capacitor.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: June 14, 2005
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AG
    Inventors: Moto Yabuki, Andreas Hilliger
  • Patent number: 6903919
    Abstract: A multilayer ceramic electronic component is prepared by covering a capacitor element with a thermoplastic resin layer that is mounted on a substrate by soldering. The thermoplastic resin layer is molten due to the heat required for soldering. The molten resin layer flows to expose external electrodes of the electronic component. The exposed external electrodes are soldered to electrodes of the substrate. In the resultant mounting structure, the thermoplastic resin layer covers substantially the entire surface except for the soldered portion of the electronic component and a portion of the solder.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: June 7, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takayuki Kayatani, Shinichi Kobayashi
  • Patent number: 6903921
    Abstract: In a chip-type solid electrolytic capacitor including a capacitor element, anode terminal and cathode terminal are electrically connected to the capacitor element. A casing resin covers the capacitor element and the anode and cathode terminals. Each of the anode and cathode terminals has a bottom mount surface to be mounted on a circuit board and an exposed surface substantially perpendicular to the bottom mount surface and exposed at a side surface of the casing resin. Each of the exposed surfaces is subjected to plating to have a plated portion.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 7, 2005
    Assignees: NEC Tokin Corporation, NEC Tokin Toyama, Ltd.
    Inventor: Masami Ishijima
  • Patent number: 6903915
    Abstract: Variable capacitive device, such as a capacitor, controllable in voltage Vc including at least one first armature (L) and one second armature (R), the armatures being separated by an insulation layer (D) including several conducting aggregates separated from each other. The use of the capacitor according to the invention in a resonant circuit.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: June 7, 2005
    Assignee: Thales
    Inventors: Alain Friederich, Frédérich Nguyen Van Dau, Albert Fert, Henri Jaffres
  • Patent number: 6899470
    Abstract: Systems and techniques are described for fabricating a low-loss, high-strength optical transmission line. In one described technique, a first fiber is spliced to a second fiber at a splice point. The spliced fibers are loaded into a heat treatment station, where a gas torch flame is used to thermally treat a splice region including the splice point, with the thermal treatment reducing splice loss between the first and second fibers. While heating the splice region, a dry gas is purged around the torch flame during the heat treatment process to avoid water at the surface of the spliced fibers. According to further described techniques, a purging gas is fed to the torch flame to purge dust particles from the flame, and after the heat treatment has been completed, the torch flame is used to restore the glass surface of the spliced fibers. Additionally described are torch assemblies for fabricating low-loss, high-strength optical fiber transmission lines.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: May 31, 2005
    Assignee: Fitel USA Corp.
    Inventors: David John DiGiovanni, Torben E. Veng
  • Patent number: 6900976
    Abstract: A variable capacitor element including: a buried electrode layer of a conductivity type different from a semiconductor substrate; a wiring layer connected to the lead portion of the buried electrode layer; a pair of capacitive insulating films that are formed as regions having mutually opposing adjacent sides in a plane shape on a portion of the buried electrode layer excluding the lead portion; an insulator layer formed on the border region of each outside of the pair of capacitive insulating films in a direction perpendicular to the adjacent sides; a pair of conductor layers formed both on the respective capacitive insulating films and on the respective insulator layers; and wiring layers that are connected respectively to lead portions of the pair of conductor layers above the insulator layer. The capacitance value between the buried electrode layer and each of the conductor layers can be changed by changing the voltage between the buried electrode layer and the conductor layers.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: May 31, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Hiraoka, Hiroki Kojima
  • Patent number: 6898070
    Abstract: A transmission line capacitor includes at least two side-by-side capacitor portions spaced apart between a separating portion all contained in a single monolithic body. Such transmission line capacitors provide specific capacitor functionality for parallel transmission lines in a printed circuit board environment, while also maintaining a desired impedance value between the transmission paths. The transmission line capacitors offer both biasing functionality for blocking undesired DC voltages as well as AC coupling functionality for passing AC voltage signals with preserved data integrity. A first embodiment may be formed with a dielectric material having a relatively low dielectric constant, allowing high capacitor “height” with fixed spacing between distinct capacitive structures. Another embodiment may be formed with a relative high K dielectric and then slotted with an air gap between capacitive structures.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: May 24, 2005
    Assignee: AVX Corporation
    Inventors: George Korony, Andrew P. Ritter
  • Patent number: 6898069
    Abstract: A multilayer electronic component of the present invention includes dielectric layers (7) and internal electrode layers (5) that are alternatively laminated. The internal electrode layers (5) are exposed alternatively to opposite sides in a laminating direction. The multilayer electronic component has at both ends thereof external electrodes (3) connected to the internal electrode layers (5), and the thickness of a connected end of the internal electrode layers (5) with the external electrodes (3) is greater than the thickness of a non-connecting end. Therefore, even if the internal electrode layers (5) are thinned, the multilayer electronic component is excellent in electrical connection property between the internal electrode layer (5) and the external electrodes (5), thereby obtaining high electrostatic capacity.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: May 24, 2005
    Assignee: Kyocera Corporation
    Inventors: Katsuyoshi Yamaguchi, Nobuhiro Higashihara, Hideto Sakoda
  • Patent number: 6894887
    Abstract: A multi-layer capacitor is highly downsized and increased in capacity. A method for manufacturing the multi-layer capacitor includes, in the same vacuum chamber, forming a dielectric layer, a surface of the dielectric layer, forming a pattern in a metal electrode, forming the metal electrode on the dielectric layer, and treating a surface of the metal electrode. In this method, etching of the dielectric layer flattens a recessed part generated by an electrical insulation part.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: May 17, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arai, Yuichiro Yamada
  • Patent number: 6891104
    Abstract: The present invention is directed to a weatherproof electrical outlet box assembly for shielding and protecting electrical components from moisture comprising a faceplate for attaching to an outlet box, the faceplate being substantially planar, and perimetrically bounded by a substantially rectangular side edge, the faceplate having at least one aperture for receiving an electrical component and; the faceplate including a first hinge socket and a second hinge socket extending respectively from the side edge in substantially orthogonal orientation.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: May 10, 2005
    Assignee: Thomas & Betts International, Inc.
    Inventor: Cong Thanh Dinh
  • Patent number: 6891716
    Abstract: A capacitor includes an anode body, a dielectric layer adjacent to the anode body, a cathode layer adjacent to the dielectric layer, and an enclosure that substantially encloses the anode body, the dielectric layer, and the cathode body. The enclosure has an upper side and an underside and is made of a castable material. The capacitor includes an anode contact having a contact section on the underside of the enclosure, an anode conductor that connects the anode body to the anode contact, and a cathode conductor that contacts the cathode layer and that exits the enclosure. The cathode conductor is a plate having holes at a portion of the cathode conductor inside the enclosure. The holes are at least partially filled with castable material.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: May 10, 2005
    Assignee: EPCOS AG
    Inventors: Jörg-Rudolf Maier, Hans-Georg Keck
  • Patent number: 6891715
    Abstract: A capacitor is formed on an interlayer insulating film formed on a semiconductor substrate. The capacitor includes a bottom electrode made of platinum, a capacitor insulating film made of SrTaBiO (SBT) containing an element absorbing hydrogen such as titanium, for example, in grain boundaries, inter-lattice positions or holes, and a top electrode made of platinum.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 10, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takumi Mikawa, Yuji Judai, Shinichiro Hayashi
  • Patent number: 6891713
    Abstract: Reduced degradation to capacitor properties is disclosed. A hydrogen storage layer is provided over at least a portion a top capacitor electrode. The hydrogen storage layer absorbs and stores hydrogen, preventing hydrogen from diffusing to the capacitor. The hydrogen storage layer has, for example, lanthium nitride, titanium zirconium nitride, amorphous sm—co, nanostructured carbon, or a combination thereof.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: May 10, 2005
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventors: Bum Ki Moon, Gerhard Beitel
  • Patent number: 6891712
    Abstract: A device for generating an inhomogeneous electrical field includes first and second electrodes. The first electrode may be a portion of a sphere, a cone, a paraboloid, a cylinder; a hollow sphere, a hollow cone, a hollow paraboloid, or a hollow cylinder. The second electrode may be a portion of a sphere, a cone, a paraboloid, a cylinder, a hollow sphere, a hollow cone, a hollow paraboloid or a hollow cylinder. The first and second electrodes are aligned to produce an inhomogeneous electric field when charged with a voltage potential and generate a gravitational effect. The second electrode may be at least partially concentric with said first electrode.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: May 10, 2005
    Assignee: PST Associates, LLC
    Inventors: Douglas G. Torr, Jose G. Vargas
  • Patent number: 6888716
    Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: May 3, 2005
    Assignee: Intel Corporation
    Inventors: Richard Scott List, Bruce A. Block, Mark T. Bohr
  • Patent number: 6888717
    Abstract: An electrolyte for a capacitor and capacitor containing the electrolyte. The electrolyte has up to about 85%, by weight, water, up to about 65%, by weight organic solvent and an acid defined by HOOC—(CH2)x—COOH wherein x is 3, 5, 7 or 9, and ammonium hydroxide.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: May 3, 2005
    Assignee: Kemet Electronics Corporation
    Inventors: John Tony Kinard, Brian John Melody, David Alexander Wheeler