Abstract: In order to provide dielectric ceramic composition having low IR defect rate and high relative dielectric constant even when the multilayer ceramic capacitor is made thinner, dielectric ceramic composition including a main component expressed by a composition formula {{Ba(1-x)Cax}O}A{Ti(1-y-z)ZryMgz}BO2 and subcomponents of Mn oxide, Y oxide, V oxide and Si oxide is provided. In the above formula, A, B, x, y and z are as follows: 0.995?A/B?1.020, 0.0001?x?0.07, preferably 0.001?x<0.05, 0.1?y?0.3 and 0.0005?z?0.01, preferably 0.003?z?0.01.
Abstract: A solid electrolytic capacitor of the present invention has a structure where respective anode sections of capacitor elements are joined to an anode lead frame by resistance welding via a through hole formed in the anode lead frame. Current thus collects to the through hole during the welding to break a dielectric oxide film layer to expose aluminum foil, and the molten aluminum collects into the through hole. Stable welding work is therefore allowed without splashing the aluminum, and a solid electrolytic capacitor having high welding strength, high reliability, and reduced ESR can be obtained.
Type:
Grant
Filed:
August 19, 2003
Date of Patent:
January 31, 2006
Assignee:
Matsushita Electric Industrial Co., Ltd.
Abstract: An electrode body 100 of a solid electrolytic capacitor component includes a foil-like aluminum substrate 2 whose surface is roughened or enlarged and which is formed with an aluminum oxide film the surface thereof as an insulating oxide film, two foil-like aluminum substrates 3a,3b whose surfaces are not roughened, and two foil-like copper substrates 4a,4b as a metal electric conductor for constituting a lead electrode. On the whole surface of the foil-like aluminum substrate 2, an anode electrode 14 including a solid high molecular polymer electrolyte layer 11, a graphite paste layer 12 and a silver paste layer 13 is formed. The thus constituted solid electrolytic capacitor component 110 is accommodated in a substantially closed space defined by a first insulating substrate 21 and a second insulating substrate 22, thereby fabricating a three-terminal type solid electrolytic capacitor.
Abstract: A feedthrough terminal assembly for an active implantable medical device utilizes to establish a reliable electrical connection between capacitor electrode plates, via inner surface metallization of a capacitor aperture, and an associated terminal pin 10, which passes at least partially therethrough. The inserts are preferably resiliently flexible, such as a spring, to establish this connection. The insert also serves to establish a mechanical connection between the capacitor and the terminal pin.
Type:
Grant
Filed:
March 30, 2005
Date of Patent:
January 17, 2006
Assignee:
Greatbatch-Sierra, Inc.
Inventors:
Robert A. Stevenson, Richard L. Brendel, Christine Frysz, Haytham Hussein, Matthew A. Dobbs
Abstract: Electrolytic capacitors having low equivalent series resistance and low leakage current are described. The electrolytic capacitors include a solid electrolyte layer of a conductive material in particular a conductive polymer, and an outer layer that includes binders, polymeric anions and conductive polymers (e.g., polythiophenes). Also described is a method of preparing electrolytic capacitors that involves forming the conductive polymer of the solid electrolyte layer in situ by means of chemical oxidative polymerization or electrochemical polymerization. Electronic circuits that include the electrolytic capacitors are also described.
Type:
Grant
Filed:
October 13, 2004
Date of Patent:
January 17, 2006
Assignee:
H.C. Starck GmbH
Inventors:
Udo Merker, Klaus Wussow, Friedrich Jonas
Abstract: An integrated circuit substrate having embdedded passive components provides a reduced cost and compact package for a die and one or more passive components. An insulating layer of the substrate is embossed or laser-ablated to generate apertures for insertion of a paste forming the body of the passive component. A resistive paste is used to form resistors and a dielectric paste is used for forming capacitors. A capacitor plate may be deposited at a bottom of the aperture by using a doped substrate material and activating only the bottom wall of the aperture, enabling plating of the bottom wall without depositing conductive material on the side walls of the aperture. Vias may be formed to the bottom plate by using a disjoint structure and conductive paste technology. Connection to the passive components may be made by conductive paste-filled channels forming conductive patterns on the substrate.
Type:
Grant
Filed:
December 12, 2002
Date of Patent:
January 17, 2006
Assignee:
Amkor Technology, Inc.
Inventors:
Ronald Patrick Huemoeller, Sukitano Rusli
Abstract: The invention relates to the dielectric composition on the basis of barium titanate (BaTiO3) that is present with Ba(Zn1/3Nb2/3)O3 in a perovslite structure, which dielectric composition exhibits an average grain size d50 in the range of 0.2 ?m to 0.5 ?m and a crystallite size d10 below 0.3 ?m.
Abstract: A solid electrolytic capacitor formed with a dielectric coating and a solid electrolyte layer successively formed on a surface of an anode body, wherein the solid electrolyte layer includes a conductive polymer containing at least a tetrahydronaphthalenesulfonate ion and a naphthalenesulfonate ion as dopants or a conductive polymer containing at least a tetrahydronaphthalenesulfonate ion and a benzenesulfonate ion as dopants. As a result, a solid electrolytic capacitor having a low ESR and a good heat resistance is provided.
Abstract: A multilayer capacitor includes a multilayer body as a main body of the multilayer capacitor, in which a plurality of internal electrodes and stacked dielectric layers each interposed between the internal electrodes are disposed and dielectrics are disposed on an outer periphery side of the plural internal electrodes, the multilayer body being formed in a rectangular parallelepiped shape with a width dimension of 2 mm or less, wherein: margin portions, in which no internal electrode exists, between end faces of the multilayer body and end portions of the internal electrodes are disposed on both end sides of the internal electrodes respectively; and a margin ratio which is a ratio of a dimension of each of the margin portions to the width dimension of the multilayer body is set to a percentage within a range of 10% to 25% per one-side margin portion of the multilayer body.
Abstract: In a capacitor 10, a first electrode 21, a valve metal layer 22, a dielectric layer 23, a chemical polymerization film 24 (a first solid electrolytic layer), a conductive organic material layer 61, an electrolytic polymerization film 25 (a second solid electrolytic layer) and a second electrode 31 are provided on a base material 11, and the conductive organic material layer 61 is obtained by applying and caking a paste-like conductive organic material 60 onto the chemical polymerization film 24.
Abstract: An electrolyte for an electrical double layer capacitor and an electrical double layer capacitor using the electrolyte are disclosed. The electrolyte has a low coefficient of viscosity, high conductivity, and high withstand voltage, and excels in long term reliability. The electrolyte for an electrical double-layer capacitor comprises a dimethyl carbonate and a compound of the following formula (1), wherein, m and n individually represent a natural number of 3-7, and X is a counter anion.
Type:
Grant
Filed:
March 29, 2005
Date of Patent:
December 27, 2005
Assignees:
Honda Motor Co., Ltd., Japan Carlit Co., Ltd.
Abstract: A dielectric layer is formed on a first metal layer, the dielectric layer is formed with many concave portions at the upper surface. A second metal layer is formed on the dielectric layer, the second metal layer is formed with a convex portion at a position corresponding to each of many concave portions. A capacitances is generated between the first and second metal layers. The capacitor element is composed of the first metal layer, the dielectric layer and the second metal layer. The first and second metal layers are used as power supply interconnection, the capacitor element is connected between a pair of power supply interconnections. Further, the first metal layer is connected to reference voltage, and the second metal layer is used as a pad electrode. By doing so, a capacitor element is connected between the pad electrode and the reference voltage.
Abstract: A vacuum variable capacitor includes an energization bellows arranged in a vacuum vessel and having ends mounted to a movable-electrode support plate and a movable side-end plate, respectively, a heat shielding bellows arranged inside the energization bellows and outside a slide-guide support and having ends mounted to the movable-electrode support plate and the movable side-end plate, respectively, and a cooling pipe interposed between the two bellows and for preventing transfer of heat generated in the energization bellows.
Abstract: Capacitor material for use in forming capacitors, is disclosed. More specifically, the invention is directed to capacitors formed from this material that have one or more discrete electrodes (314), each electrode (314) being exposed to at least two thicknesses of dielectric material (300). These electrodes (314) are surrounded by wider insulative material (312) such that the material can be cut, or patterned into capacitors having specific values. A single electrode can form a small value capacitor while still providing a larger conductive area for attaching the capacitor to associated circuitry. The thin dielectric (310) can be a tunable material so that the capacitance can be varied with voltage. The tunability can be increased by adding thin electrodes that interact with direct current.
Type:
Grant
Filed:
May 9, 2002
Date of Patent:
December 13, 2005
Assignee:
nGimat Co.
Inventors:
Andrew T. Hunt, Mark G. Allen, David Kiesling
Abstract: An electronic device comprises a silicon substrate (base material), an underlying insulating film formed on the silicon substrate, a capacitor constructed by forming a bottom electrode, a capacitor dielectric film, and a top electrode sequentially on the underlying insulating film, and a voltage supply circuit for supplying a voltage with a bipolar waveform to at least one of the bottom electrode and the top electrode, wherein an amplitude of the voltage is set to 5×105 d (V) or less (d: an interval (cm) between the top electrode and the bottom electrode). Accordingly, an electronic device and a method of applying a voltage to a capacitor, capable of prolonging a lifetime of a capacitor by preventing degradation of a capacitor dielectric film are provided.
Type:
Grant
Filed:
December 16, 2004
Date of Patent:
December 13, 2005
Assignee:
Fujitsu Limited
Inventors:
John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
Abstract: A solid electrolytic capacitor has a structure in which a dielectric layer and a metal layer are formed in this order on the surface of an anode. The anode is composed of a porous sinter of tantalum particles. The dielectric layer is composed of a dielectric oxide film formed by anodizing the surface of the anode in an aqueous solution consisting of phosphoric acid, for example. The metal layer is formed by preparing a silver paste by mixing silver particles having an average particle diameter of not larger than 0.05 ?m, a protective colloid, and an organic solvent, and applying the silver paste on the surface of the dielectric layer, and drying the silver paste at a temperature of 150° C. or higher. Further, the anode is connected with an anode terminal, and the metal layer is connected with a cathode terminal through a conductive adhesive.
Abstract: Flat electrolytic capacitors, particularly, for use in implantable medical devices (IMDs), and the methods of fabrication of same are disclosed. The capacitors are formed with an electrode stack assembly comprising a plurality of stacked capacitor layers each comprising an anode sub-assembly of at least one anode layer, a cathode layer and separator layers wherein the anode and cathode layers have differing dimensions that avoid electrical short circuits between peripheral edges of adjacent anode and cathode layers but maximize anode electrode surface area.
Type:
Grant
Filed:
August 13, 2004
Date of Patent:
November 8, 2005
Assignee:
Medtronic, Inc.
Inventors:
Mark D. Breyen, Andrew Michael Jacobs, Anthony W. Rorvick, Paul A. Pignato
Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.
Type:
Grant
Filed:
March 12, 2003
Date of Patent:
November 8, 2005
Assignee:
Intel Corporation
Inventors:
Kishore K. Chakravorty, Thomas S. Dory, C. Michael Garner
Abstract: A capacitor includes a capacitor main body having a front surface on which a semiconductor device is to be mounted and a rear surface at which the capacitor main body is to be mounted on a first main surface of a circuit substrate, a plurality of internal electrodes disposed within the capacitor main body, and a plurality of via conductors penetrating the capacitor main body between the front surface and the rear surface and electrically connected to the internal electrodes, wherein the capacitor main body has a first dielectric layer located on a side of the capacitor main body closer to the front surface and a second dielectric layer located on a side of the first dielectric layer closer to the rear surface, the second dielectric layer having a higher thermal expansion coefficient and a higher dielectric constant than the first dielectric layer.
Type:
Grant
Filed:
June 8, 2004
Date of Patent:
November 1, 2005
Assignee:
NGK Spark Plug Co., Ltd.
Inventors:
Jun Otsuka, Manabu Sato, Yukihiro Kimura
Abstract: An electrolytic capacitor with a polymeric housing in the form of a pocket defining a chamber, with an opening along a selected edge. The opening has opposed sides that are sealed together to provide a seam. A number of conductive layers are positioned within the chamber, and a feed-through conductor element has a first end electrically connected to the layers. An intermediate portion of the feed through passes through the seam, and an external portion extends from the housing. The housing may be vacuum formed high density polyethylene, with the feed-through contained in an elastomeric sleeve having a flattened cross section to be readily received in the seam, and to accommodate thermal expansion differences between the housing and the feedthrough. The device may be manufactured by inserting a stack of layers in the pocket, and thermally welding across the opening of the pocket on a single weld line.