Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.

Abstract: An electroluminescent display apparatus can include a driving thin film transistor on a substrate, the driving thin film transistor including a gate electrode, a source electrode, a drain electrode, and an active region; a capacitor electrode facing the gate electrode; a first electrode electrically connected to the source electrode; a light emitting layer on the first electrode; and a second electrode on the light emitting layer, wherein the gate electrode and the capacitor electrode extend in a vertical direction with respect to a surface of the substrate.

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

Abstract: A method of manufacturing a light emitting device, including: providing a first structure including: providing a lead frame which includes providing a metal plate including a plurality of pairs of first and second metal parts, each metal part including an upper surface, a lower surface, and an end surface, the end surface of the first metal part and the end surface of the second metal part of each pair are opposite to each other, and a first region including the end surface, and disposing a mask of a resist film on the first region using an electrodeposition technique, disposing a first plated layer containing gold or gold alloy on a second region including the upper surface other than the first region on at least one of the upper surface, the lower surface, and the end surface of each of the first and second metal parts using a plating technique, and removing the resist film, providing a resin molded body molded integrally with the lead frame with parts of a lower surface of the lead frame being exposed, in

Abstract: A method of manufacturing a silicon carbide device includes: forming a trench in a process surface of a silicon carbide substrate that has a body layer forming second pn junctions with a drift layer structure, wherein the body layer is between the process surface and the drift layer structure and wherein the trench exposes the drift layer structure; implanting dopants through a bottom of the trench to form a shielding region that forms a first pn junction with the drift layer structure; forming dielectric spacers on sidewalls of the trench; and forming a buried portion of an auxiliary electrode in a bottom section of the trench, the buried portion adjoining the shielding region.

Abstract: A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.

Abstract: A III-Nitride LED which utilizes n-type III-Nitride layers for current spreading on both sides of the device. A multilayer dielectric coating is used underneath the wire bond pads, both LED contacts are deposited in one step, and the p-side wire bond pad is moved off of the mesa. The LED has a wall plug efficiency or External Quantum Efficiency (EQE) over 70%, a fractional EQE droop of less than 7% at 20 A/cm2 drive current and less than 15% at 35 A/cm2 drive current. The LEDs can be patterned into an LED array and each LED can have an edge dimension of between 5 and 50 ?m. The LED emission wavelength can be below 400 nm and aluminum can be added to the n-type III-Nitride layers such that the bandgap of the n-type III-nitride layers is larger than the LED emission photon energy.

Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

Abstract: Disclosed is a method for fabricating CSP LEDs.

Abstract: An LED package structure includes a multilayered circuit board, a plurality of lighting elements, a control unit, a reflecting unit, a package unit, a plurality of test paths and a plurality of operation paths. The multilayered circuit board includes a plurality of testing pads, a first electrical connecting pad and a plurality of second electrical connecting pads. The lighting elements are disposed on the multilayered circuit board. The control unit is electrically connected to the lighting elements. The reflecting unit is disposed on the multilayered circuit board and surrounds the lighting elements. The package unit covers the lighting elements. The test paths are in electrical connection with the first electrical connecting pad, the lighting elements and one of the testing pads. The operation paths are in electrical connection with the first electrical connecting pad, the control unit, the lighting elements and one of the second electrical connecting pads.

Abstract: The invention relates to a method for producing an electronic system, comprising: a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member to form a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports; a step of depositing at least one electronic component on the lower redistribution layer; and a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors of the electronic component to the inner connection ports of the lower redistribution layer.

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.

Abstract: The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.

Abstract: A semiconductor device includes a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate, a probe pad formed on the dielectric stack, a test key embedded in the semiconductor device and a single via string stacking extending along a direction from a level of the probe pad to the semiconductive substrate and electrically connecting the periphery of the probe pad to the test key. A semiconductor device includes a semiconductive substrate, a dielectric stack, a probe pad, a test key, an extension segment electrically connected to the periphery of the probe pad and laterally extending from the probe pad from a top view, and a single via string stacking extending along a direction from the probe pad to the semiconductive substrate and electrically connecting the extension segment to the test key. The single via string stacking and the probe pad are laterally offset from a top view.

Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

Abstract: A semiconductor device includes a substrate, a first semiconductor chip on the substrate, a first adhesive material on the first semiconductor chip, a spacer chip on the first adhesive material, a second adhesive material on the spacer chip, a second semiconductor chip on the second adhesive material, and a resin material that covers the first and second semiconductor chips and the spacer chip. The spacer chip has a first region with which the resin material comes in contact is roughened and a second region that is different from the first region.

Abstract: A method for producing a light emitting device, including: integrally molding plural leads with a molded resin portion comprising a resin composition containing a thermosetting resin or a thermoplastic resin, so as to prepare a substrate having a concave portion having a side surface and a bottom surface; disposing a light emitting element on the bottom surface of the concave portion; forming a film including a metal oxide on the side surface of the concave portion and an upper surface of the substrate; disposing a sealing resin composition containing an addition curing silicone resin composition containing an organopolysiloxane containing a functional group capable of performing a crosslinking reaction and an aryl group in one molecule, and an organic modified silicone oil that is unreactive with the organopolysiloxane, in the concave portion; and curing the sealing resin composition to form a resin package.