Patents Examined by Antonio B Crite
  • Patent number: 11676947
    Abstract: The present disclosure provides a driving substrate, a method for preparing the same, and a flexible display device. The driving substrate includes: a base substrate; a stress buffer layer located on the base substrate; a wiring structure located on a surface of the stress buffer layer away from the base substrate, a thickness of a wiring of the wiring structure in contact with the stress buffer layer being greater than a threshold; a first insulating layer located on a surface of the wiring structure away from the base substrate; a plurality of electronic components on a surface of the first insulating layer away from the base substrate; the electronic component being connected to the wiring structure through a via hole penetrating the first insulating layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 13, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jianguo Wang
  • Patent number: 11675344
    Abstract: A method for generating a report regarding prioritizations of industrial automation devices in an industrial system may include determining a first score for each of the industrial automation devices. The first score represents a relative importance of each of the industrial automation devices. The method may also include determining a second score for each of one or more parts of each of the industrial automation devices. The second score represents a relative importance of each of the parts with respect to each other. The method may also include generating the report comprising the parts, the industrial automation devices, the first score for each of the industrial automation devices, the second score for each of the parts, or any combination thereof, wherein the report is organized according to the first score, the second score, or based on a combination of the first score and the second score.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 13, 2023
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Andrew Wilber, Jeromy Scott Humphrey, Michael James Lanphear
  • Patent number: 11677060
    Abstract: Provided is a method for transferring and bonding devices. The method includes applying an adhesive layer to a carrier, arranging a plurality of devices, attaching the arranged devices to the carrier, applying a polymer film to a substrate, aligning the carrier to which the plurality of devices are attached with the substrate, bonding the plurality of devices to the substrate by radiating laser, and releasing the carrier from the substrate to which the plurality of devices are bonded.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: June 13, 2023
    Assignee: ELECTRONICS AND TELEOCMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jiho Joo, Yong Sung Eom, Gwang-Mun Choi, Kwang-Seong Choi, Chanmi Lee, Ki Seok Jang
  • Patent number: 11677052
    Abstract: A semiconductor light-emitting device includes a semiconductor light-emitting element having a supporting substrate and a sealing member located above the supporting substrate, a mounting substrate on which the semiconductor light-emitting element is mounted in such a manner that the sealing member faces the mounting substrate, and a sealing part that integrally covers a part of the supporting substrate and a side surface of the sealing member and seals the semiconductor light-emitting element and the mounting substrate.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 13, 2023
    Assignee: Nikkiso Co., Ltd.
    Inventors: Hiroyasu Ichinokura, Tadaaki Maeda, Kazuyoshi Sakuragi
  • Patent number: 11677047
    Abstract: In accordance with certain embodiments, electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g., light-emitting or a light-detecting element) suspended in the binder and within the aperture of the frame.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: June 13, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Michael A. Tischler, Alborz Amini, Thomas Pinnington, Henry Ip, Gianmarco Spiga
  • Patent number: 11670748
    Abstract: A light emitting diode (LED) package structure includes a circuit board, a reflective cup, a LED chip and a lens structure. The reflective cup is mounted on the circuit board, wherein the reflective cup and the circuit board collectively form a concave cup with an opening. The reflective cup has a first metal ring in the concave cup. The LED chip is mounted on the circuit board and within the concave cup. The lens structure has a second metal ring configured to join the first metal ring to cover the opening.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: June 6, 2023
    Assignee: Lextar Electronics Corporation
    Inventors: Chang-Han Chen, Chun-Peng Lin, Lung-Kuan Lai
  • Patent number: 11670739
    Abstract: A light emitting diode (LED) package structure including a first light emitting portion, a second light emitting portion, a partition, and a surrounding wall is provided. The first light emitting portion includes a first LED chip emitting a first initial light, and the first initial light passes through the first light emitting portion to form a first white light. The second light emitting portion includes a second LED chip, a third LED chip, and a fourth LED chip. The partition is disposed between the first light emitting portion and the second light emitting portion. The surrounding wall is disposed around the partition, the first light emitting portion, and the second light emitting portion. The first white light has a view angle offset less than 1 degree.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: June 6, 2023
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Hao-Wei Hong, Chen-Hsiu Lin, Tsung-Kang Ying
  • Patent number: 11664358
    Abstract: A display apparatus includes a driving substrate, a first light-emitting diode element, a first connection element, a second connection element, a first insulation pattern, and a reflective pattern. The driving substrate has a first pad, a second pad, a third pad, and a connection area. The first connection element is electrically connected to a first electrode of the first light-emitting diode element and the first pad of the driving substrate. The second connection element is electrically connected to a second electrode of the first light-emitting diode element and the second pad of the driving substrate. The first insulation pattern is disposed on the first light-emitting diode element, the first connection element, and the second connection element. The reflective pattern is disposed on the first insulation pattern.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 30, 2023
    Assignee: Au Optronics Corporation
    Inventors: Chung-Chan Liu, Pin-Miao Liu
  • Patent number: 11664354
    Abstract: An electronic device is provided in this disclosure. In some embodiments, the electronic device includes two display panels, a first filling element, and a second filling element. The two display panels adjoin each other. The first filling element and the second filling element are disposed between the two display panels, and a material of the first filling element is different from a material of the second filling element. In some embodiments, the electronic device includes a protection substrate, two light emitting plates, and a filling element. The two light emitting plates adjoin each other. The protection substrate is disposed corresponding to the two light emitting plates, and the two light emitting plates emit light towards the protection substrate. The filling element is disposed between the two light emitting plates.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 30, 2023
    Assignee: InnoLux Corporation
    Inventors: Wan-Ling Huang, Chun-Hsien Lin, Yi-An Chen, Tsau-Hua Hsieh
  • Patent number: 11664339
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a first circuit layer, a first dielectric layer, an electrical device and a first conductive structure. The first circuit layer includes a first alignment portion. The first dielectric layer covers the first circuit layer. The electrical device is disposed on the first dielectric layer, and includes an electrical contact aligning with the first alignment portion. The first conductive structure extends through the first alignment portion, and electrically connects the electrical contact and the first alignment portion.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 30, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Patent number: 11664309
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A structure extending vertically through a memory stack including interleaved conductive layers and dielectric layers is formed above a substrate. A first dielectric layer is formed on the memory stack. An etch stop layer is formed on the first dielectric layer. A first contact is formed through the etch stop layer and the first dielectric layer and in contact with an upper end of the structure. A second dielectric layer is formed on the etch stop layer. A second contact is formed through the second dielectric layer and in contact with at least an upper end of the first contact.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 30, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Hongbin Zhu, Juan Tang, Zi Qun Hua
  • Patent number: 11664483
    Abstract: A light-emitting device includes a micro light-emitting diode chip (micro LED chip), a first electrical connecting layer, a second electrical connecting layer and a housing layer. The micro LED chip includes a light exit surface, a bottom surface opposite to the light exit surface and first and second electrodes located on the bottom surface. The first and second electrical connecting layers respectively connect to the first and second electrodes and extend along two opposite sidewalls to two sides of a perimeter of the light exit surface. The housing layer encloses the micro LED chip and the first and second electrical connecting layer. The light exit surface of the micro LED chip and top surfaces of the first and second electrical connecting layers are not enclosed by the housing layer.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 30, 2023
    Assignee: Lextar Electronics Corporation
    Inventors: Shiou-Yi Kuo, Jian-Chin Liang, Jo-Hsiang Chen, Chih-Hao Lin
  • Patent number: 11664322
    Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
  • Patent number: 11662065
    Abstract: A manufacturing method of an LED filament and a manufacturing method of a bulb are provided. The steps are as follows: step S1, preparing a support; step S2, fixing chips; step S3, performing a first baking and performing a lighting test after cooling; step S4, dispensing a glue in which a semi-finished product is covered with a covering glue, and a viscosity of the covering glue used is 5000 to 50000 mPa·S; and step S5, performing a second baking. According to the disclosure, the preparation of the LED filament is completed through support preparing, chip fixing, the first baking, dispensing and the second baking, and the covering glue selected during dispensing has good fluidity, and the fluorescent powders mixed in the covering glue can be uniformly dispersed, thus preventing precipitation or agglomeration and ensuring good light distribution.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: May 30, 2023
    Assignee: Hangzhou Hangke Optoelectronics Co., Ltd.
    Inventors: Qianjun Yan, Yaoxing Wang, Zhaozhang Zheng, Lingli Ma
  • Patent number: 11664323
    Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 11664480
    Abstract: A semiconductor package substrate includes a semiconductor housing space including a mounting surface being provided on a bottom side and configured to mount a semiconductor light-emitting element, and a reflective wall being provided around the mounting surface and configured to reflect light emitted from the semiconductor light-emitting element to be mounted on the mounting surface; a mounting region being provided at a rim portion and configured to mount a lid member for covering the semiconductor light-emitting element; and a flow-suppressing portion separating the mounting region and the reflective wall spatially in such a manner that a joining member joining the lid member to the rim portion is suppressed from flowing from the mounting region into the semiconductor housing space.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: May 30, 2023
    Assignee: Nikkiso Co., Ltd.
    Inventors: Hiroyasu Ichinokura, Kazuyoshi Sakuragi
  • Patent number: 11574872
    Abstract: Package structure and method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge die, and a second encapsulant. The first encapsulant laterally encapsulates the first die and the second die. The bridge die is electrically connected to the first die and the second die. The second encapsulant is located over the first die, the second die and the first encapsulant, laterally encapsulating the bridge die and filling a space between the bridge die and the first die, between the bridge die and the first encapsulant and between the bridge die and the second die. A material of the second encapsulant is different from a material of the first encapsulant.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 11569425
    Abstract: A method of making a surface-mountable pixel engine package comprises providing an array of spaced-apart conductive pillars and an insulating mold compound laterally disposed between the conductive pillars on a substrate together defining a planarized surface. Pixel engines comprising connection posts are printed to the conductive pillars so that each of the connection posts is in electrical contact with one of the conductive pillars. The pixel engines are tested to determine known-good pixel engines. An optically clear mold compound is provided over the planarized surface and tested pixel engines. Optically clear mold compound is adhered to a tape and the substrate is removed. The optically clear mold compound, the insulating mold compound, the conductive pillars, the optically clear mold compound, and the tested pixel engines are singulated to provide pixel packages that comprise the pixel engines and the known-good pixel engines are transferred to a reel or tray.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 31, 2023
    Assignee: X Display Company Technology Limited
    Inventors: Christopher Andrew Bower, Matthew Alexander Meitl, Glenn Arne Rinne, Justin Walker Brown
  • Patent number: 11562988
    Abstract: An area light source, a method for manufacturing the same and a display device are provided. The area light source includes: a first conductive structure and a second conductive structure arranged opposite to each other; and a light-emitting layer arranged between the first conductive structure and the second conductive structure and including a plurality of light-emitting chips insulated from each other. A first electrode of each light-emitting chip is electrically connected to the first conductive structure, and a second electrode of each light-emitting chip is electrically connected to the second conductive structure.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 24, 2023
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY GROUP CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jian Sang, Haiwei Sun, Junjie Ma
  • Patent number: 11563171
    Abstract: A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang