Abstract: An automated method and apparatus are used for creating data processing application programs in programmer oriented languages such as COBOL from atomic or fundamental program building blocks, i.e., individual programming language statements, based on information provided by the user at the terminal. Host/peripheral input/ output subroutines are selected from a library of existing I/O subroutines, based on the type of I/O indicated by the user; and, the application program can incorporate existing subroutines, tables, files, etc. so as to avoid having to create code which has already been created. The system also provides for a level of validity checks and interactive editing of the application program as it is being created at the terminal. A user may thus change some aspect of the application program, or correct a logic error which has been detected by the system, interactively without having to start over from scratch after compiling the source program to detect errors.

Abstract: A word processor includes a keyboard, a cathode-ray tube, a first and a second storage devices, a central processing unit, and an internal storage. The first storage device stores information about the image displayed on the CRT. A floppy disk in which a program for a personal computer is stored can be installed in the second storage device. When the power supply of the word processor is put to work, the CPU ascertains whether such a floppy disk is installed in the second storage device. If installed, the CPU causes the present system to operate as an ordinary word processor. If not installed, the CPU allows the printer to operate in quick response to the input from the keyboard in accordance with the program stored in the ROM of the internal storage device.

Abstract: A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has separate portions, one that retrieves operands and the other that retrieves instructions. When the fetch unit fetches a conditional branch instruction, it may continue to prefetch "branch not taken" instructions using the instruction fetch portion. The fetch unit initially uses the operand fetch portion to prefetch "branch taken" instructions. If it is determined that the branch is not taken, the prefetch operation is aborted, otherwise the prefetch operation is allowed to continue to provide the next instruction used by the processor.

Abstract: The system includes a fetching circuit which sequentially fetches instructions to be executed. Certain of the instructions require that a predetermined condition code be present prior to being executed and certain of the instructions cause a condition code to be generated as a result of their execution. Condition code generators are provided for generating condition codes in response to execution of the instructions causing generation of condition codes. A circuit is also provided which is responsive to the sequentially fetched instructions for individually determining which of the instructions is to cause generation of a condition code, and which of the condition code generators is to generate a condition code for each of the determined instructions. The determined condition code generators are monitored, and a decision is made as to when a valid condition code has been generated by the monitored generator. A signal is produced when a valid condition code is generated.

Abstract: A method for facilitating the interchange of data in a UNIX* file between two UNIX processes being run concurrently on two virtual machines in a page segmented virtual memory virtual machine type data processing system. A Shared Copy-On-Write (SCOW) command is created for the UNIX type operating system which when executed in response to a system call from one processes causes the specified UNIX file to be mapped to a unique segment of the virtual memory. A map node data structure is established for storing the ID of the unique segment and for maintaining a count value of the number of user sharing the unique segment. A system call to the SCOW command by the second process involving the same UNIX file checks the map node data structure to see if the file is currently mapped for the SCOW mode. Subsequent instructions in the application programs which are run concurrently on the virtual machines operate on the copy of the file in the unique segment so that any data that is changed, i.e.

Abstract: An apparatus for preparing and playing back a duplicated disk containing software as a program so that a customer will be able to use the disk for a predetermined trial period. The duplicated disk is impressed with information relating to this system in the form of a usage count, a locking status and an output code. The usage count is written on the disk and determines the number of times the disk can be used by a customer. The output code identifies a locking code whereby after the allocated number of uses is over, the vendor can unlock the disk to allow unlimited use. The lock code determines whether or not the disk is subjected to the above noted trial usage period. The usage count which is impressed on the disk is detected during each time the disk is used and the usage count is decremented by one until the predetermined number of uses has been accommodated.

Abstract: Method and apparatus for interconnecting the processing cells of a parallel processing machine configured in a two-dimensional rectangular array in which each cell includes a plurality of ports, each port having a unique port address, and a plurality of cells have similarly addressed ports. The cells are interconnected, via the cell ports, to form cell clusters having a central cell and eight neighboring cells such that a plurality of neighboring cells share a common connection to the central cell and further such that no two similarly addressed ports are coupled to one another. During a data transfer operation, in accordance with the single instruction multiple data (SIMD) format, each cell transmits data from one port and receives data from another port such that all cells transmit data from similarly addressed ports and receive data at similarly addressed ports to provide data transfer throughout the array in a uniform direction.

Abstract: The topography of a sixteen bit CMOS microprocessor chip including circuitry for enabling it to emulate, under software control, a prior art 6502 microprocessor includes an N-channel minterm logic section including 498 "vertical" diffused minterm lines across which 32 "horizontal" metal lines from an instruction register and a timing generator pass and make selective contact to separate polycrystalline silicon gate electrodes to effectuate a first level of instruction op code decoding. The resulting minterm signals are inverted by a row of CMOS inverters, the outputs of which are connected to polycrystalline lines extending into an N-channel sum-of-minterm section. "Horizontal" metal sum-of-minterm conductors contact various N-channel field effect transistors in the sum-of-minterm region.

Abstract: A general purpose register including two input ports and two output ports, each port being addressed by an independent addressing circuit. The general purpose register includes a number of internal registers, and the provision of four independent addresses enables data to be written into two internal registers while data is being read out of two internal registers. The general purpose register also includes circuitry for transferring data from the input ports directly to the output ports without entering the data into the internal registers. Interchanging of bytes of data input words is also accomplished by the general purpose register. The internal registers, the four independent addressing circuits, the data transferring circuitry and additional undedicated circuitry are integrated into a single chip.

Abstract: A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.

Abstract: In a multiple-block-per-entry buffer memory (BS) of the swap or store-in type, a swap-out buffer (SOB) having a capacity for at least a block is provided. On the occasion of replacing, a memory access sequence control responds to change bits and validity bits associated with an entry to be replaced as well as the block address designated for memory access so as to execute the data transfer from a main memory (MS) to BS in preference to the sweeping-out of data from BS to SOB so long as the block to be replaced need not be stored in MS. If the block to be replaced needs to be stored, the sweeping-out into SOB is executed with the utmost priority, and the data transfer from MS is then executed in preference to the sweeping-out of any other blocks to be stored into MS.

Abstract: In a lock control for a shared storage, each storage controller (SC) includes circuitry (LKA) for holding the addresses locked by any of the storage utilizing units connected thereto and circuitry (FLKA) for holding a copy of the contents of LKAs of the other SCs. When one storage utilizing unit connected to one SC issues a storage access request, its requested address is compared with the contents of the LKA and FLKA in the associated SC, thus determining whether or not the requested address is locked by any other storage utilizing unit connected to that particular SC or by any of the storage utilizing units connected to the other SCs. Each storage utilizing unit may include a FLKA.

Abstract: A system allows a workstation to utilize the resources of another workstation without requiring the presence of an operator on the second workstation. These resources can include memory and processor cycles, and I/O devices including disk, diskette, printer, and communications ports. When an operator is present at the second workstations, resources in excess of those required at the second workstation can also be used by a first workstation. Messages are displayed on the display of the second workstation warning that resources there are being utilized to prevent inadvertent powering off of the second workstation. In addition, jobs may be automatically started at the second workstation when the workstation is powered on, without requiring any additional action or logging on by the operator.

Abstract: An electronic postage meter includes two non-volatile memories. One of the non-volatile memories is utilized for storing in historical sequence in respective registers the transaction information for each of a predetermined number of transactions which have occurred prior to the last transaction. This memory is accessed at the time of each transaction. The real-time transaction information may be sequentially written over the earliest information in the registers. The other non-volatile memory stores cumulative data upon power-down.

Abstract: A method for use in a virtual memory data processing system employing a pageable External Page Table data structure for recording current status and disk address information for each virtual page in said system, provides improved system performance when a large number of virtual pages are to be operated on in the same manner. In accordance with the method, each page of External Page Table entries can record a predetermined number of entries (512), depending on the byte capacity of each virtual page (2,048) and the size of each entry (4 bytes). One page of 512 entries correspond to 1 megabyte of virtual storage (512.times.2,048) and also appears as one entry in a pinned External Page Table. The pinned External Page Table is referred to as the "XPT of the XPT," and has the same format as the pageable XPT. A 256 megabyte segment of virtual memory is representable in the XPT of the XPT by 256, 4 byte entries, or one-half of a page.

Abstract: A data processing apparatus employing a DMA system has a newly added circuit having a register in addition to the normal combination of a host processor, a memory and a DMA controller. The added circuit is provided between the host processor and the DMA controller. The host processor produces a setting signal by itself for setting a bus request signal into the register of the added circuit. The added circuit applies the bus request signal set in the register to the host processor without an access from the DMA controller. The host processor receives the bus request signal and sends a bus usage grant signal to the added circuit when the host processor does not need to use a bus or after a processing using the bus has been completed, and electrically cuts off itself from the bus. The DMA controller requests a bus usage to the added circuit when a DMA transmission is required.

Abstract: An apparatus directs storage requests from a processor through a storage controller to storage. The storage controller contains address comparators which are uninitialized, i.e., they contain no address identifiers. As a result, logic within the storage controller is used to direct these storage requests until the address comparators become initialized. The storage controller directs the first and all subsequent storage requests to a read only storage if the first storage request is for a load, or read, operation. Conversely, the storage controller directs the first and all subsequent storage requests to a random access memory if the first storage request contains a store, or write, operation. An initialization program contained in an I/O device is loaded into the random access memory at the time the first storage request containing a store operation is made.

Abstract: The preferred embodiment shown involves forming the memory system of B memory banks, where B is preferably a prime number, but may be a nonbinary number, i.e., B=2.sup.X, where X is a positive integer, and where the requested address=(Q+R)B. The address translation system for each requestor seeking access to the memory system includes a ROM and an adder. The ROM is comprised of two ROMs, Q ROMa and Q ROMb. ROMb stores in successive memory locations a first portion Qb of the memory system address and Q ROMa stores in successive memory locatins a second portion Qa of the memory system address. An adder sums the data, Qa+Qb, stored in the addressed memory locations of Q ROMa and Q ROMb while Q ROMa stores in successive memory locations a Bank R portion that specifies the one of the B banks in which the sum Qa+Qb addresses the selected memory address in the selected memory bank of the memory system.

Abstract: A transportable bus control architecture for single-chip microprocessors consists of an interface control unit that is logically independent of the associated co-resident, common clock-driven microprocessing unit. This independence allows the interface control unit logic to be used with a variety of microprocessing units. The interface control unit presents an external appearance that is compatible with the peripheral devices of a specific microprocessor referred to as the "compatible microprocessor", thereby making available to an associated co-resident microprocessing unit the support devices of the compatible microprocessor. The interface control unit can also access other external devices not related and transparent to the devices of the compatible microprocessor. The interface control unit is logically divided into an execution section and a control section.

Abstract: A simulation security device for a data entry keyboard of a computer is operative with an input-output unit and a keyboard of the computer. The device includes plural memories and a switching assembly which are operatively coupled to row and column signals generated by the keyboard. One memory stores coded call instructions of a working program, and a second memory stores call instructions of the working program and addresses of these instructions, there being an address counter associated with the second memory. The memories are connected via the input-output unit and the switching assembly for responding to row and column signals of the keyboard to permit the transmission of call instructions to the computer so as to prevent any transmission of coded instructions of the keyboard during an initialization and a transmission of call instructions.