Abstract: A magnetic tape system includes a driving unit (1) including a magnetic head (14), reels (11, 12) for winding a magnetic tape (16) thereon and a drive portion for driving the reels; a drive control unit (2, 20, 21) for controlling the drive unit; and a prefetch control unit (3) having a first memory for prefetching a plurality of commands from the host controller and a second memory for temporarily storing data from the host controller or data read out from the magnetic tape. The drive unit is operated through the drive control unit according to the commands stored in the first memory and the results of the operation are reported to the host controller.

Abstract: Races and hazards in simulated logic designs are more easily detected if the logic simualtor is able to warn the designer of the presence of glitches. A glitch wall occur at the output of a logic device if an input condition causes the output to begin to change but the input condition is not present for sufficient time to allow the output to reach its stable state. The logic evaluator is the component of the logic simulator which is responsible for determining the output of a simulated device when the inputs to that device are known. The glitch detecting logic evaluator according to the present invention provides glitch detection by forcing the simulated device output to the undefined state when the device inputs change in a manner which does not allow the change to propagate to the output before a subsequent change occurs. The algorithms are designed for implementation in hardware for high performance logic simulation.

Abstract: Logic simulation is performed using special purpose hardware which operates in either one of two simulation modes. The machine allows detailed timing simulation where each device may be programmed with a delay time of zero, one, or multiple simulation time units. In addition, the machine supports zero and unit delay simulation in a high performance "unit delay" mode. The logic simulation function is partitioned into six sub-functions which are implemented in a single stage of a six-stage pipeline. The pipeline stages which implement the multi-unit delay time queue management may be switched to perform a different algorithm for unit delay simulation. The machine is able to perform extremely fast functional circuit testing and to perform detailed timing simulation without changing the circuit "netlist".

Abstract: A spelling correction system compares a correctly spelled word with an incorrectly spelled word to determine the degree of substitutability. If the system determines that the words are highly similar, the system flags the correct word as exclusively substitutable for the incorrect word. If the system determines the words are of moderate similarity, the correct word is flagged as a possible substitute for the incorrect word.

Abstract: A method for allocating and optimizing register assignments during compiling of source into executable code in either a scalar or vector processor uses a pebble game heuristic played on each basic block dependency graph for local optimization. Like variable analysis and loop unrolling are used for global optimization.

Abstract: A parallel processing computer comprises at least a memory for storing program as well as data and instructions for executing the program, a plurality of functional units, a node driving register for indicating executable instructions which are allowed to be executed by the functional units, and a mode register giving information to the functional unit as to whether the processing to be executed is of serial nature or parallel nature.

Abstract: When one of general registers has a register number indicated by a renewal instruction and should be renewed to a result of execution by an arithmetic unit of an execution time measured in terms of machine cycles for the renewal instruction, a register (91) holds the register number as a held number. From a machine cycle number representative of the execution time, a counter (95) is counted down in each machine cycle to successively provide decreasing numbers. Coincidence circuits (97, 98) find coincidence between the held number and two register numbers indicated by a current instruction which is preceded by the renewal instruction and for which two operands should be read from the general registers of the two register numbers. When the coincidence is found, execution of the current instruction is suspended. Otherwise, the operands are read. The suspension is released when the counter is counted down to zero.

Abstract: An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.

Abstract: An information storage/retrieval system stores information to be retrieved in a storage device having a first memory and a second memory. The first memory stores therein main records each containing an index word data, a derivative pattern code and information pieces while the second memory stores therein auxiliary records each containing a derivative pattern code and supplemental word data. Each derivative pattern code represents a group of words whose primary parts such as word stem parts are commonly combinable with the same remaining parts such as affix parts. Thus, each index word data is qualified by the accompanying derivative pattern code, and the supplemental word data includes data corresponding to the above-mentioned remaining parts. An information retrieval is made by searching in a first memory with respect the primary part of a keyword taken from, for example, its head and then in a second memory with respect to the remaining part of the keyword, thereby identifying the keyword.

Abstract: A method and apparatus expands the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required.

Abstract: In a microprogram controller by pipeline control which includes a memory for storing a microprogram and a program counter for representing the address of the memory, a microprogram controller includes means for judging whether or not a branch condition of a branch microinstruction is satisfied and means for converting the microinstruction fetched from the memory to a NOP (No Operation) microinstruction from the output of the next step of the memory till the outputs after a plurality of steps by the affirmation output of the judging means. When the affirmation output is obtained from the judging means, part of the memory output is loaded into the program counter and when the negation output is obtained, a value as the sum of a current value plus 1 is loaded into the program counter.

Abstract: An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.

Abstract: In a Distributed Database System (DDS), database management and transaction management are extended to a distributed environment among a plurality of local sites which each have transaction server, file server, and data storage facilities. The Materialization and Access Planning (MAP) method of a distributed query, update, or transaction is an important part of the processing of the query, update, or transaction. Materialization and access planning results in a strategy for processing a query, update, or transaction in the distributed database management system (DSDBMS). Materialization consists of selecting data copies used to process the query, update, or transaction. This step is necessary since data may be stored at more than one site (i.e., computer) on the network. Access planing consists of choosing the execution order of operations and the actual execution site of each operation. Three access planning methods are used: General (Response), General (Total) and Initial Feasible Solution (IFS).

Abstract: An apparatus and a method for interfacing a commercially-available programmable communication interface (PIC) with a magnetic swipe reader or a wand type reader. The invention modifies the raw signals of the magnetic wand and magnetic swipe readers by removing noise and selecting the appropriate reader and track, stretching the clock pulses of the reader, and latching data into a flip-flop until the data is strobed into the PIC.

Abstract: An electronic apparatus includes power source for supplying power, a key input unit for inputting key instructions, a memory for memorizing the key instructions, a generator for generating a power off cancel instruction to be invalidated the power-off of the power supplied from the power source in response to at least one of the key instructions or at least one of the memorized instructions memorized by the memory, a detector for detecting the output of the power off cancel instruction generator, and a controller for controlling the power source in response to the output of the detector.

Abstract: The current microinstruction of a micromachine enables a selected one of a plurality of conditions to select one of a plurality of microaddress qualifiers to be combined with a specified base microaddress to form the next microaddress for the micromachine.

Abstract: A memory management system method increases the size of a segment in blocks of 64K virtual pages in response to the system detecting that the requested page has been protected. The conventional UNIX type System Calls create and open files in virtual memory. All pages are protected "read only" until a SHMAT type System Call is made to operate on a page at a specific address. At that point in the process, a protection exception is recognized by the system and the UNIX kernel takes control to remove the protection and update the appropriate data structures to reflect the new status of the page and the addresses in real memory where the page may be found. Segments containing mapped files are also extended by the method.

Abstract: An arbitration system for a machine tool control has multiple processors and a local memory associated with each processor. The arbitration system allows one processor to access data stored in a foreign memory, i.e. the local memory of a second processor so that the time required for one processor to gain access to data used by another processor is relatively short. The system includes an external arbitration control which arbitrates requests for access to a foreign memory from each of the processors. The system also includes a plurality of local arbitrators each associated with a particular processor to arbitrate requests for access to its processor's bus and memory from a plurality of users including the external arbitration control, a DRAM controller and a direct memory access controller.

Abstract: A data processing system which includes a central processing unit (CPU) to which is connected an I/O bus and a memory bus is disclosed. The data processing system further includes an I/O controller and a video control section. The I/O controller includes a terminal control section which is connected to the CPU through an RS232 Cable, an I/O control section which is connected to the I/O bus over a single line and a single processor for managing both the terminal control section and the I/O control section. The I/O control section includes a plurality of interface and control subsystems each for use with a separate peripheral device and an I/O bus interface and control subsystem. The terminal control section includes a video control section interface through which data is sent directly to the video control section over a separate line, and a keyboard interface for interfacing the terminal control section to a keyboard.

Abstract: A multi-processing device includes three or more processing systems, each having a processor and a corresponding main memory connected to each other by means of an individual memory bus. The multi-processing device also includes a common memory bus connectable to all the processors and all the main memories of the respective systems, an asynchronism detection circuit connected to the respective processors to produce an asynchronism detection signal indicating which system or systems are in asynchronous state, and a device control circuit responsive to the asynchronism detection signal to send a common memory bus select signal to the main memory of each failed system to change its bus connection from the individual memory bus to the common memory bus. The device control circuit also generates a master designation signal for allowing an arbitrary processor of the normal non-faulty systems to be designated as a master processor, and a copy request signal to the respective processors.