Abstract: Periodic checkpoints are taken of the state of a computer system and its virtual memory. If a system crash occurs, the machine state can be rolled back to the checkpoint state and normal operation restarted. Pages of virtual memory are timestamped to indicate whether they are included in the checkpoint state. Modifications made after the checkpoint time are discarded when the system state is rolled back to the saved checkpoint state. Some recordkeeping is maintained outside of the virtual memory address space in order to assist with the recovery process.

Abstract: A document generating system which includes an input device for inputting document data, a heading candidate extraction section for extracting, as a heading candidate, the word corresponding to the heading stored in a heading dictionary from the document data input at the input section. A heading decision section is implemented in the system for checking the heading candiate, that was extracted by the heading candidate extraction section according to a heading rule stored in a heading rule dictionary and for deciding whether the heading candidate is a heading. Also, a document architecture decision section is implemented in the system for checking the heading decided by the heading decision section according to document architecture rules stored in a document architecture rule dictionary. The architecture decision section is for determining the heading as satisfying the document architecture rule as a true heading, and the heading not satisfying the document architecture rule as being false heading.

Abstract: List operation on a vector in which the number of an element of a vector operand is represented by an element of another vector operand is to be performed with a general-purpose computer system having no vector registers. List vector elements are read out from a memory by adding at addresses determined sequentially by adding by adding values of a request vector increment register to a list vector address. A value resulting from the bit shift of the element is stored in a second operand increment register. A second vector element is read out from the memory at the address corresponding to a value resulting from addition of the content of the second operand increment register to the second operand initial address register, the element being then stored at the memory location of the address given by a value resulting from the addition of the value of the first operand vector increment register to the first operand address.

Abstract: A graphics display apparatus employs a general purpose or main microprocessor providing general control of the apparatus including receiving high-level graphic orders defining a desired graphic image from a host processor and dedicated graphics microprocessor connected to receive low-level graphic orders from the general microprocessor along a pipeline constituted by a shared buffer store. Pipeline control logic controls the pipeline by blocking the graphics processor which generally operates more quickly than the general processor until the latter has completed computation of all the low-level orders associated with a particular high-level order. The front-of-screen performance can be further improved by backing up the pipeline to repeat certain low-level orders rather than by obtaining these repeated orders by recomputation. Graphics hardware controlled by the graphics processor loads appropriate bit patterns into an all points addressable refresh buffer for subsequent display on a cathode ray tube monitor.

Abstract: A main microprocessor A (11) provides data to a display formatter microprocessor B (12) via a data bus (13). Microprocessor B provides data and latch (activity) pulses (34A) to a visual display (27) comprising a number of individual display devices (28-30) which are sequentially excited by data obtained from microprocessor B. An external activity detector (38), in response to an absence of the latch pulses of microprocessor B for a predetermined time, generates a reset signal (40) for resetting the microprocessor A. In response to being reset, microprocessor A provides an output control signal (at 20) which results in the resetting of the microprocessor B. If microprocessor B determines that microprocessor A is not properly providing data to it, microprocessor B will terminate generating the latch pulses (34A). The preceding configuration results in each of the microprocessors effectively monitoring the operation of the other microprocessor so as to insure proper system operation.

Abstract: In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to segments to the bulk memory without replacement is accomplished in accordance with an age since first write algorithm.

Abstract: A low overhead way for insuring that only routines of sufficient privilege can execute on a secured page of memory in an hierarchial computer system, and for raising the privilege level of a low privilege process in an orderly and secure way is presented. This is done through the execution of a single "gateway" branch instruction standing between a procedure call by a lower privileged routine, such as a user program, and an operating system itself.

Abstract: An apparatus determines the order of data communication between a plurality of peripheral devices that wish to do so and a central processor unit. Determination is made according to one of a number of selectable priority schedules. The apparatus is modifiable by programmed control so that certain of the peripheral devices can have their priorities reconfigured depending upon changing circumstances.

Abstract: A small-sized office computer includes a cathode ray tube displaying a plurality of desired ruled line frames and desired characters or other information on the display during execution of business processes. The screen information is stored on a recording medium such as a floppy disc. Means are provided for specifying parameters in response to introduction of information into respective ruled line frames and programs are prepared using the parameters. The screen information is read and displayed through execution of said programs.

Abstract: A prefetching mechanism for a system having a cache has, in addition to the normal cache directory, a two-level shadow directory. When an information block is accessed, a parent identifier derived from the block address is stored in a first level of the shadow directory. The address of a subsequently accessed block is stored in the second level of the shadow directory, in a position associated with the first-level position of the respective parent identifier.With each access to an information block, a check is made whether the respective parent identifier is already stored in the first level of the shadow directory. If it is found, then a descendant address from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids, with a high probability, the occurrence of cache misses.

Abstract: An operator interactive translation system for translating sentences in a first language to sentences in a second language includes a separate memory for storing translated words in the second language as learned words corresponding to input words in the first language, upon being indicated as correct equivalents by the user. For each subsequent translation using sentence construction and morpheme analysis, the learned word stored in the buffer memory is selected as the first translation each time the specific input word in the first language appears in a sentence to be translated.

Abstract: The computing installation comprises a plurality of digital computers and at least a terminal unit, for instance a printer, suitable for use in cooperation with any one of the computers. Each computer may deliver a request for access to the terminal. In response, a connection is established between the computer which issued the request and the terminal if the latter is free. Simultaneously, access to the terminal unit by the other computers is prevented for a predetermined time period or for the duration of the connection between the terminal unit and the computer which first issued an access request.

Abstract: An incremental garbage collector for use in conjunction with a virtual memory, operates on selected generations of an area upon objects which are contained in a semispace, oldspace or newspace, and during the garbage collection process, all accessible objects are copied from the oldspace to the newspace. The garbage collection process occurs in four phases. In the "flip" phase oldspace and newspace of each generation are exchanged. In the "trace" phase, the pointers which are part of a root set of the generation being collected are traced and all oldspace objects referenced by the pointers are copied to newspace, and the pointers in the root set are updated. All copied objects are then "scavenged" to update any pointers in the cells of the copied objects, and to copy to newspace all oldspace objects referenced by those pointers. Finally a "cleaning oldspace" phase is performed as a low-priority background process to purge the entries for the virtual pages on which "obsolete" pointers reside.

Abstract: A register recovering system for a data processor having a group of general-purpose registers includes a saving register for saving the content of the general-purpose register; a control register for storing discrimination information for the general-purpose register; a setting unit for setting the discrimination information at the control register, based on instruction information of a machine code to be processed by the data processor; and a setting unit for setting the content of the saving register to the general-purpose register in accordance with the discrimination information stored in the control register.

Abstract: A microprogrammed data processing system uses a plurality of control stores to control the data processing system in response to a macroinstruction sequence. Between each control store is a latch element resulting in a given address being applied to each control store at different system clock cycles. The corresponding microinstruction segment from each control store is therefore provided at different clock cycles, making it possible to coordinate the microinstruction segment with the corresponding flow of data through the central processing unit. The use of a plurality of control stores can reduce the number of gate elements needed to delay microinstruction segments.

Abstract: A microprocessor controlled mass storage controller is used as an interface for mass storage devices which are shared by a plurality of stand-alone microcomputer systems. The microprocessor controlled mass storage controller has a system interface which maintains communications with a host microcomputer; a dedicated microprocessor which maintains the internal control of the controller and a network interface which maintains an access to the external network. Data transparency and integrity are achieved through the simulation by the controller of the mass storage device characteristics and responses.

Abstract: A data processing system includes a plurality of data processing modules coupled to a bus and to a set of control lines. These modules request the use of the bus by sending respective sequences of at least two binary numbers during successive cycles on the control lines in synchronization with each other. On the control lines the numbers are logically ORed together. Each module terminates the sending of its numbers if, during any one of the successive cycles, the logical OR is greater than twice the number which the module itself is sending. A module uses the bus only if, during each of the successive cycles, the logical OR does not exceed the number which the module itself sends.

Abstract: A system for operating a computing machine is provided with a plurality of executable functions, each being identified by a respectively associated function symbol. In one embodiment, the data stored in a memory of the computing machine is organized into files, each such file further containing additional data which corresponds to one of the function symbols, and a selected file name which identifies the file with respect to which the executable function is to operate. In a preferred embodiment, one of the function symbols in the file is selected, and execution thereof is subsequently commanded. Preferably, the machine is returned to a state which permits selection of a further executable function. Thus, the invention forms a coupling between a transaction process and an execution process, in the form of a loop.

Abstract: An information processing system includes a processor responsive to instructions for performing operations. The processor includes instruction queue for fetching and storing instructions in advance of execution and the system is responsive to certain of the instructions for causing execution of a corresponding sequence of instructions. A prefetch monitor includes circuitry for detecting instructions which may result in the execution of a corresponding sequence of instructions. The prefetch monitor further includes an instruction substitution circuit which is responsive to the detecting circuitry for inhibiting the reading of following instructions from a memory to the processor and is responsive to instruction fetching operation of the processor for reading null instructions to the processor.

Abstract: The interface apparatus couples a video recording device to the parallel data channel of a computer system and also to the computer video output circuitry, so that both digital information (such as computer programs or data files) and analog information (such as video signals for displaying on a television monitor) may be stored on the same video recording medium. The apparatus permits storage of both digital information and human readable information in a convenient back-to-back relationship. The interface permits the computer video monitor to directly display stored or live video broadcasts, without computer intervention. The invention allows the display of graphic, photographic and motion picture information in analog format thereby eliminating information lost through digitizing. An automatic search mode permits the computer to direct the video recording device to search for a predetermined location on the recording medium at high speed without human intervention.