Abstract: A memory access apparatus in which a data memory has a plurality of data storing areas is accessed by a CPU in accordance with a sequential access method. A window latch and an adder are provided between the memory and CPU. Addresses stored in the window latch and addresses issued by the CPU are added together to create a memory access address. The window latch is so set that a data storing area within the data memory corresponding to an inputted spelling of a word is accessible by the CPU.

Abstract: A pattern generator and controller arrangement operats for controlling the component parts of an MRI system. The arrangement comprises a plurality of channels including a main control channel and output channels. The arrangement receiver instructions from the system CPU which then leaves the control and outputting to the arrangement, thereby avoiding the necessity of a large expensive CPU to operate the system with versatility and speed.

Abstract: A high performance terminal input/output subsystem for connecting a multiplicity of user devices to a multi-user computer includes a single-board host adapter which is mounted in a single bus slot in the host computer card cage and provides the communication between the subsystem and the host computer. One or more multiple terminal, intelligent cluster controllers is remotely located from and coupled to the host adapter by means of a coaxial cable. The cluster controllers are multidropped from the coaxial cable in daisy chain fashion. Communication between the host adapter and cluster controllers utilizes a high speed communication line employing a 2.5 Mbit/second baseband, token-passing, serial bus, local area network protocol. Each cluster controller provides local terminal connections for 8 or 16 user devices.

Abstract: Apparatus and method for accelerating a validity response provided by a floating point unit assures the validity of the present state of a condition code and an interrupt signal before the completion of a floating point arithmetic instruction whose result affects the condition code and interrupt signal. The accelerated validity response is derived from an evaluation of the exponents, signs, and fractions contained in the operands of a currently-executing floating point arithmetic operation which is made prior to or during execution of the instruction. Also provided is the capability of setting the condition code prior to the completion of certain add class floating point instructions where one of those instructions stimulates an early validity response. An accelerated interrupt request is also provided in synchronism with an accelerated validity response for certain floating point add and subtract instructions.

Abstract: A system for collection of data and entry of the data to a host computer has a portable, hand held, data collector for collecting data and a stationary data relay for receiving the data from the data collector and for transmitting the data to the host computer. The portable hand held data collector includes a case of a size and shape to be held by one hand during use, a keyboard for inputting the data, displaying for displaying the data, memory for storing the data and an interface for transmitting the data to external. The data relay includes a case shaped to set the portable data collector thereon, of first interface for receiving the data transmitted from the data collector and of said interface for comunicating bidirectionally to the host computer.

Abstract: A word processor includes a work station having a keyboard and a display device, a main unit for forming a text file in accordance with input commands entered by the keyboard, an external memory unit for storing the text file, a standardized character memory for storing dot patterns of characters having standardized style, a modified character memory for storing dot patterns of characters having modified style, and a printer for printing out a document in accordance with the text file. When a plurality of documents to be delivered to different addresses are formed in accordance with the same text file, different characters in respective documents are replaced by modified characters to form text files having different modified characters. Then the plurality of documents are printed in accordance with respective text files having different modified characters, so that these documents can be distinguished from one another.

Abstract: A cache memory circuit is responsive to a read request to fetch a data block in a block transfer from a main memory to a cache memory. A sequence of data units into which the data block is divided is successively assigned to a plurality of cache write registers. The assigned data units are simultaneously moved to one of sub-blocks of the cache memory during each of write-in durations with an idle interval left between two adjacent ones of the write-in durations. Each state of the sub-blocks is monitored in a controller. During the idle interval, a following read request can be processed with reference to the states of the sub-blocks even when it requests the data block being transferred. In addition, a read address for the following read request may be preserved in a saving address register to process another read request.

Abstract: A data processing system comprising at least two operating systems (OS1, OS2) for virtual machines, a supervisory operating system, i.e., a control program (CP) for controlling the operating systems, control registers (CR0, CR1, ---) and an extended control register (ECR) having a special bit. When a control register operating instruction (LCTL or STCTL) is executed by one of the operating systems, the special bit has a first value and the operating system directly accesses the control register. When the other of the operating systems attempts to execute such a control register operating instruction, the special bit has a second value and an interruption is generated in the supervisory operating system.

Abstract: A memory pointer circuit includes a plurality of counters and a programmable logic array for controlling the counters to generate addresses for an acquisition memory. The programmable logic array directs a lower counter to generate a repeating sequence of addresses to store data before an event occurs, each pass through the sequence causing previously written data to be overwritten until an event has occurred and is stored in memory. The programmable logic array then directs the upper counters to increment and the lower counter to generate a following sequence of addresses to store data after the event occurs. Once the following sequence is complete, the upper counters are again incremented and the repeating sequence of addresses is again generated. The procedure is repeated to store multiple clusters of data and events in the acquisition memory. Once the acquisition memory is full, the stored data and events can be saved or overwritten.

Abstract: In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Abstract: The system provides a relatively inexpensive raster-scan type graphics system capable of real time operation, utilizing logic-enhanced pixels within an image buffer, permitting parallel (simultaneous) calculations at every pixel. A typical implementation would be as custom VLSI chips. Each cell of the image buffer corresponds to a pixel of the display, and a processor at each cell enables calculation of the pixel color and the like for each polygon in the image covering that same pixel (cell) of the display. In the sequence of most general applications, each polygon is operated upon in sequence, and the image is built up as the polygons are processed without the necessity of sorting.

Abstract: A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.

Abstract: An apparatus provides a sequence detected signal indicating that a synchronization sequence occurring at regular intervals in a stream of data has occurred or should have occurred. The apparatus includes logic for detecting the synchronization sequence, logic responsive to the detection logic for producing the sequence detected signal when the detection logic detects the sequence, and logic for producing the sequence detected signal at a fixed time after the synchronization sequence should have occurred. If the synchronization sequence did occur, the apparatus thus produces two sequence detected signals; however, the device receiving the sequence detected signal responds to the first sequence detected signal and ignores the second. If the synchronization sequence did not occur, the device receiving the sequence detected signal responds to the sequence detected signal produced by the logic responsive to the timing apparatus.

Abstract: An interface circuit in a modular electronic system includes duplex control-signal transmission lines. Modules connectable to a controller unit of the system transmit configuration data items by way of the duplex lines to the controller during a first time period, and the controller during a second time period generates module control signals in accordance with the configuration of the modules. The module control signals are transmitted to the modules on the duplex transmission lines.

Abstract: An apparatus and method employs dual checkpoint data sets for communicating system status. A journal of changed data is implemented to reduce I/O to a subsystem's shared data area on a non-volatile shared storage device. The journal provides for an increase in the amount of time that a processor may have access to the shared data area. Also, two versions of the data area are implemented in order to insure the integrity of the continuously updated data area. The two versions flip-flop depending upon which one has the most recent updates. That is, the version that has the most recent updates becomes the to-be-read-from data area and is read by the processor that currently has access to the shared data area during this series of I/O operations. The other version becomes the to-be-written-to data area and is written to by the processor that currently has access to the data area in order to update the to-be-written-to version to the current level.

Abstract: An apparatus for use with a DMA controller includes a device interface controller having therein both general and specific command programs, and device bus interface. The apparatus is arranged to intercept all communication signals between the DMA controller and a microcomputer associated therewith.

Abstract: A control system for a disk cache memory is disposed between a main memory unit and a disk unit for storing a record of data from the disk unit. The control system is designed such that when an input/output instruction is issued from a CPU while data loading is being performed from the disk unit to the cache memory, it interrupts the data loading once so that an input/output instruction from the CPU can be executed, thereby considerably reducing the time of wait for execution of the input/output instruction.

Abstract: A data logging device has a data memory unit (11) and a transducer interface unit (1). The data memory unit has an internal power source (12), an integrated circuit memory component (23) for storing data under the control of a microprocessor (18) in the memory unit, light emitting diodes (14, 21) for indicating the amount of data stored in the memory component and the power source state. A connector component (19) connects the memory component to receive data from the transducer interface unit. The transducer interface unit (1) has a plurality of ports (2) for connection of remote transducers and an analog to digital converter (5) for translating signals received from the ports into data signals which can be transferred to the memory component in the data memory unit through a connector component (9) connected to the connector component (19) of the data memory unit.

Abstract: A portable electronic memorandum device is placed in the password set mode by operating switch Sl. In this mode, if the correct password is set, the secret mode is set up and the secret data is displayed. If user forgets the password, switch Sc is operated in the error display mode. By this operation, the password and the secret data are both cleared, so that secrecy of the secret data can be protected.

Abstract: A mechanism for determining when the contents of a block in a cache memory have been rendered stale by DMA activity external to a processor and for marking the block stale in response to a positive determination. The commanding unit in the DMA transfer, prior to transmitting an address, asserts a cache control signal which conditions the processor to receive the address and determine whether there is a correspondence to the contents of the cache. If there is a correspondence, the processor marks the contents of that cache location for which there is a correspondence stale.