Patents Examined by Arnold M. Kinkead
  • Patent number: 10812018
    Abstract: An oscillator start-up circuit and methodology for oscillator start-up is disclosed. The circuit includes a reference bias switch coupled to a reference node and a load node of a transconductor of an oscillator. The reference bias switch is responsive to a control signal for start-up of the oscillator and operable to close at a first time prior to start-up of the oscillator to maintain a voltage at the reference node equal to a voltage at the load node prior to application of bias to the transconductor. The reference bias switch is further operable to open at a second time subsequent to the first time. In one embodiment, a separate reference bias voltage is applied to a reference node of the transconductor.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 20, 2020
    Assignee: Arm Limited
    Inventor: Alexandru Aurelian Ciubotaru
  • Patent number: 10812087
    Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 20, 2020
    Assignee: Mixed-Signal Devices Inc.
    Inventors: Tommy Yu, Avanindra Madisetti
  • Patent number: 10804912
    Abstract: A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Utku Seckin, Simone Gambini, Benjamin W. Cook
  • Patent number: 10804844
    Abstract: A voltage controlled oscillator includes a variable capacitance circuit having a plurality of variable capacitance elements, each having a capacitance that is a function of a tuning voltage, two or more oscillator core circuits, each operable over a specified frequency band, and inductive elements connected between the variable capacitance circuit and the oscillator core circuits.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: October 13, 2020
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Ronan Brady, Shane Collins
  • Patent number: 10804848
    Abstract: The present disclosure describes a low-power, low-phase-noise (LPLPN) oscillator. The LPLPN oscillator includes a resonator load, an amplifier stage, and a loop gain control circuit. The resonator load is structured to resonate at a primary resonant frequency. The amplifier stage is coupled with the resonator load to develop a loop gain that peaks at the primary resonant frequency. The loop gain control circuit is coupled with the amplifier stage, and it is structured to regulate the loop gain for facilitating the amplifier stage to generate an oscillation signal at the primary resonant frequency and suppress a noise signal at a parasitic parallel resonant frequency (PPRF).
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: October 13, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Seong-Ryong Ryu, Ali Kiaei
  • Patent number: 10804905
    Abstract: Using a burn-in operational amplifier (opamp) for a phased locked loop (PLL) regulator including activating a voltage stress mode for an integrated circuit comprising a PLL regulator for a PLL, wherein the PLL regulator comprises thin-oxide transistors, and wherein activating the voltage stress mode for the integrated circuit comprises applying an elevated voltage to an input of the PLL regulator; and enabling, during the voltage stress mode, a burn-in opamp coupled to the input of the PLL regulator, wherein enabling the burn-in opamp bias the input of the PLL regulator to a voltage lower than the elevated voltage.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: James Strom, Grant P. Kesselring, David M. Friend
  • Patent number: 10804845
    Abstract: For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 13, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subhashish Mukherjee, Kumar Anurag Shrivastava, Sreeram Subramanyam Nasum
  • Patent number: 10804910
    Abstract: A circuit device includes a phase comparison circuit that performs phase comparison between a reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage, a voltage controlled oscillation circuit that generates a clock signal, a dividing circuit that divides the clock signal and outputs the feedback clock signal, a processing circuit that sets a division ratio of the dividing circuit, a first register in which slope information of a waveform signal for spreading the frequency of the clock signal is set, and a second register in which amplitude information of the waveform signal is set. The processing circuit generates a waveform signal value based on the slope information and the amplitude information set in the first and second registers, and outputs division ratio data based on the waveform signal value and the division ratio setting value to the dividing circuit.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 13, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hideki Sato
  • Patent number: 10800271
    Abstract: A supply device for a motor vehicle has a DC/DC converter and a control device for the DC/DC converter. The DC/DC converter has first terminals and second terminals, which first terminals are configured for electrical connection to a first energy storage or a first energy source and which second terminals are configured for electrical connection to a second energy storage or a load. The DC/DC converter is configured, in a first state to enable a conversion of a first DC voltage at the first terminals into a lower second DC voltage at the second terminals and, in a second state, to carry out no conversion of a first DC voltage at the first terminals into a lower second DC voltage at the second terminals. The control device enables an energy supply at the second terminals by repeatedly changing the DC/DC converter between the first state and the second state.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 13, 2020
    Assignee: Dr. Ing. h.c. F. Porsche Aktiengesellschaft
    Inventors: Christian Vienken, Dominique Labonte, Ulrich Steinhorst, Marc Thele, Michael Schumacher
  • Patent number: 10797711
    Abstract: An oscillator includes a quartz crystal resonator and a circuit device, and the circuit device includes an oscillation circuit and a PLL circuit. The PLL circuit includes a phase comparison circuit that performs a phase comparison between the reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage based on a result of the phase comparison, and a voltage control oscillation circuit that generates a clock signal having a frequency corresponding to the control voltage, and a frequency division circuit that divides a frequency of the clock signal and outputs the feedback clock signal. An oscillation frequency of the quartz crystal resonator is higher than or equal to 200 MHz, and a phase comparison frequency of the phase comparison circuit is higher than or equal to 200 MHz.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 6, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yasunari Furuya
  • Patent number: 10790790
    Abstract: An audio amplifier system includes a delta-sigma modulator configured to receive an m-bit digital audio input signal and to generate a pulse density modulated signal based on the m-bit digital audio input signal. An analog power stage is coupled to the delta-sigma modulator to receive the pulse density modulated signal and amplify the pulse density modulated signal to generate an amplified pulse density modulated signal. A feedback circuit is coupled to the delta-sigma modulator and the analog power stage. The feedback circuit is configured to receive the amplified pulse density modulated signal and the pulse density modulated signal and to determine a digital error signal representative of a difference between the amplified pulse density modulated signal and the pulse density modulated signal. The feedback circuit is further configured to provide the digital error signal to the delta-sigma modulator for applying the digital error signal to a representation of the m-bit digital audio input signal.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 29, 2020
    Assignee: KAPIK INC.
    Inventors: Robert Neil McKenzie, William Martin Snelgrove, Wai Tung Ng
  • Patent number: 10790781
    Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an oscillation circuit, a charge pump circuit, a smoothing circuit, and a negative feedback circuit. The charge pump circuit is arranged between each of a power supply input terminal and the oscillation circuit and a power supply output terminal. The smoothing circuit is arranged between the charge pump circuit and the power supply output terminal. The negative feedback circuit is arranged on a path returning from the smoothing circuit to the oscillation circuit. The smoothing circuit includes a first zero point generation circuit.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 29, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hironori Nagasawa
  • Patent number: 10780851
    Abstract: A power source device of present disclosure includes: a first power storage element; a second power storage element that is connected in parallel to the first power storage element and that has a lower internal resistance than an internal resistance of the first power storage element and a lower storage capacity than a storage capacity of the first power storage element; an opening and closing part that is connected between the first power storage element and the second power storage element and that switches between a disconnection state and a connection state; a charge circuit that is connected to an input route of the first power storage element and that performs a step-down operation; a discharge circuit that is connected to an output route of the second power storage element and that performs a step-up operation; and a controller that controls operations of the opening and closing part, the charge circuit, and the discharge circuit.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 22, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Youichi Kageyama, Takashi Higashide, Katsunori Atago, Yugo Setsu, Hisao Hiragi
  • Patent number: 10778146
    Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Grant P. Kesselring, James Strom, Scott Trcka, Ann Chen Wu
  • Patent number: 10775748
    Abstract: Some variations provide an alkali metal or alkaline earth metal vapor cell with a solid ionic conductor and intercalable-compound electrodes. The intercalable-compound electrodes are used as efficient sources and/or as sinks for alkali metal or alkaline earth metal atoms, thus enabling electrical control over metal atom content in the vapor cell. Some variations provide a vapor-cell system comprising: a vapor-cell region configured to allow a vapor-cell optical path into a vapor-cell vapor phase; a first electrode; a second electrode electrically isolated from the first electrode, wherein the second electrode contains an intercalable compound intercalated by an element selected from Rb, Cs, Na, K, or Sr; and an ion-conducting layer between the first electrode and the second electrode. The ion-conducting layer is ionically conductive for at least one ionic species selected from Rb+, Cs+, Na+, K+, or Sr2+. The intercalable compound is preferably a carbonaceous material, such as graphite.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 15, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Christopher S. Roper, Adam F. Gross, Matthew T. Rakher, Logan D. Sorenson, John J. Vajo, Jason A. Graetz, Russell Mott, Danny Kim
  • Patent number: 10771014
    Abstract: An oscillator bias stabilization circuit and method for biasing the circuit is disclosed. The bias stabilization circuit includes a plurality of resistive dividers responsive to a control signal in the circuit. The plurality of resistive dividers are selectably connectable in the circuit to provide an adaptable equivalent resistance in response to a control signal while keeping a bias voltage produced by the circuit substantially constant as the loop gain of an oscillator is varied. The plurality of resistive dividers are coupled to a node in the oscillator that establishes the bias voltage.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Arm Limited
    Inventor: Alexandru Aurelian Ciubotaru
  • Patent number: 10763787
    Abstract: Circuit for wireless communication are provided, the circuits comprising: a first quadrature hybrid having a first in port, a first iso port, a first cpl port, and a first thru port; a first mixer having a first input coupled to the first cpl port and having an output; a second mixer have a first input coupled to the first cpl port and having an output; a third mixer having a first input coupled to the first thru port and having an output; a fourth mixer having a first input coupled to the first thru port and having an output; and a first complex combiner having inputs coupled to the output of the first mixer, the output of the second mixer, the output of the third mixer, and the output of the fourth mixer that provides first I and Q outputs based the output of the first mixer and the output of the second mixer.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 1, 2020
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Jianxun Zhu, Peter R. Kinget
  • Patent number: 10749467
    Abstract: A piezoelectric resonator unit includes a base member having a mounting surface. A piezoelectric resonator is mounted on the mounting surface and a lid member is bonded to the mounting surface such that the piezoelectric resonator is hermetically sealed in an inner space. A heat conductor is connected to a temperature sensor that detects a temperature of the piezoelectric resonator and is connected to a heating element that radiates heat onto the piezoelectric resonator. The heat conductor has a portion that is arranged in the inner space.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 18, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazuyuki Noto
  • Patent number: 10749717
    Abstract: A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Oscar Sebastian Burbano, Reuben P. Nelson
  • Patent number: 10749538
    Abstract: An oscillator arrangement having an oscillator configured to generate an oscillation signal having two half-cycles, an input configured to receive a synchronization signal including synchronization triggers, a synchronizer configured to reject a synchronization trigger received during a first part of a half-cycle and to synchronize the oscillator to a synchronization trigger received during a second part of the half-cycle, and a controller configured to prolong the second part of the half-cycle in response to receiving a synchronization trigger during the first part of the half-cycle.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Marco Bucci, Raimondo Luzzi