Patents Examined by Arnold M. Kinkead
  • Patent number: 12009786
    Abstract: A circuit device includes a waveform-shaping circuit that waveform-shapes an oscillation signal and provides an output clock signal based on a clock signal. A bias voltage output circuit of the circuit device provides a bias voltage of the oscillation signal that is input to the waveform-shaping circuit. A comparator of the circuit device compares a DC voltage obtained by smoothing the clock signal with a reference voltage. A logic circuit of the circuit device sets an adjustment value of the bias voltage. In a test mode of the logic circuit, the logic circuit changes the adjustment value to determine a set value of the adjustment value based on output of the comparator when the adjustment value is changed and stores the determined set value in a storage circuit.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: June 11, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kohei Beppu, Takehiro Yamamoto
  • Patent number: 12009826
    Abstract: Circuits, methods, and apparatus that can reduce or suppress phase noise in a frequency synthesizer. A phase-noise-suppression system can detect phase noise in an input signal, amplify the detected phase noise, subtract the detected phase noise from the input signal, and provide an output signal having reduced phase noise.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: June 11, 2024
    Assignee: Anritsu Company
    Inventors: Nikolay Shtin, Oleksandr Chenakin, Suresh P. Ojha
  • Patent number: 11989623
    Abstract: The present invention aims at enabling a gate-type quantum computer to deal with actual problems. There is provided a quantum computer including: a quantum register holding qubits, a control gate performing an operation on the quantum register, and a readout unit observing a state of the quantum register; and the quantum computer repeating longitudinal relaxation to the ground state by gradually changing Hamiltonian H(t) for a predetermined time, wherein the unitary operation determined by the Hamiltonian H(t) at each time is performed with the control gate for a time of about a longitudinal relaxation time, the quantum state is relaxed every time of about the longitudinal relaxation time, and the ground state prepared for an initial state is time-evolved to the ground state of the Hamiltonian which is defined as a problem.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: May 21, 2024
    Assignee: HITACHI, LTD.
    Inventor: Tatsuya Tomaru
  • Patent number: 11990907
    Abstract: One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 21, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Nandakishore Raimar, Brajveer Singh, Iulian Gradinariu
  • Patent number: 11984747
    Abstract: The disclosed apparatus and method is a closed loop system that obtains, stores and transfers motive energy. Preferably, the majority of the electricity generated is utilized to service a load or supplied to the grid. A portion of the electric power produced is used to recharge the batteries for subsequent use of the electric motor. The system controls and manages the battery power by controlling the charging and discharging of the battery reservoir via a series of electrical and mechanical innovations controlled by electronic instruction using a series of devices to analyze, optimize and perform power production and charging functions in sequence to achieve its purpose.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 14, 2024
    Assignee: Klepfer Holdings, LLC
    Inventors: George Mitri, Don Klepfer
  • Patent number: 11983126
    Abstract: An electronic component is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies, for reading out the quantum state of a qubit in a quantum dot. The electronic component comprises a substrate having a two-dimensional electron gas or electron hole gas. Electrical contacts connect the gate electrode assemblies to voltage sources. The gate electrode assemblies have gate electrodes, which are arranged on a surface of the electronic component, for producing potential wells in the substrate.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 14, 2024
    Assignees: Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen, Forschungszentrum Jülich GmbH
    Inventors: Matthias Künne, Hendrik Bluhm, Lars Schreiber
  • Patent number: 11984848
    Abstract: The present invention relates to a frequency generator arrangement having an oscillator for generating an oscillator signal having an oscillator frequency and an oscillator output for outputting the oscillator signal, the frequency generator arrangement further comprising a frequency multiplier coupled and/or connected to an oscillator output for generating an output signal of the frequency generator arrangement having a multiplier frequency corresponding to a multiple of the oscillator frequency, wherein the frequency multiplier comprises a frequency multiplier core directly causative of the frequency multiplication, the frequency multiplier core having a power supply, and the frequency generator arrangement having a control input for controlling the power supply to the frequency multiplier core, whereby an output power of the output signal is adjustable by controlling the power supply to the frequency multiplier core.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: May 14, 2024
    Assignee: 2pi-Labs GmbH
    Inventors: Timo Jaeschke, Simon Kueppers
  • Patent number: 11982579
    Abstract: Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 14, 2024
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Brian Hardy Cobb, Joao De Oliveira, Thomas Clark, Kenneth David Williamson
  • Patent number: 11984849
    Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: May 14, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Aniruddha Roy, Preetham Narayana Reddy
  • Patent number: 11980107
    Abstract: A quantum computing system including plural base configurations each configured including a first quantum bit group configured from first quantum bits arranged so as to form a single column without mutual coupling, a second quantum bit group configured from second quantum bits arranged so as to form a single column with adjacent ones of the second quantum bits coupled together and each of the second quantum bits coupled to the first quantum bit that is arranged in a same row, and a third quantum bit coupled to all of the second quantum bits. The plural base configurations are arranged so as to form a single column with the third quantum bits in adjacent ones of the base configurations coupled together. In a quantum computing circuit configuration, a two-dimensional cluster state or a three-dimensional cluster state is accordingly realized with two-dimensional control wiring, or surface code is accordingly realized with a pseudo two-dimensional superconducting circuit.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 7, 2024
    Assignee: Tokyo University of Science Foundation
    Inventors: Jaw-Shen Tsai, Hiroto Mukai, Keiichi Sakata
  • Patent number: 11979164
    Abstract: In a semiconductor integrated circuit, a first oscillation circuit receives a first clock signal and outputs a second clock signal synchronized with the first clock signal in frequency and phase. A second oscillation circuit receives a control signal and outputs a third clock signal having a frequency corresponding to the received control signal. A detection circuit detects a frequency difference between the second clock signal and the third clock signal. A determination circuit determines whether a frequency locked state is established between the first clock signal and the second clock signal. A control circuit varies the control signal, such that the frequency difference decreases while the frequency locked state has not been established and increases after the frequency locked state is established.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventor: Kiyohito Sato
  • Patent number: 11973465
    Abstract: An oscillator circuit is provided. The oscillator circuit includes a first oscillator, a second oscillator, and a switch matrix. The first oscillator includes a first transconductance amplifier, a second transconductance amplifier, and a first resonator. The second oscillator includes a third transconductance amplifier, a fourth transconductance amplifier, and a second resonator. The first resonator includes a first capacitor element and a first inductor element. The second resonator includes a second capacitor element and a second inductor element. The first inductor element is coupled to the second inductor element. The switch matrix includes a first switch, a second switch, a third switch, and a fourth switch.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: April 30, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Huancheng You
  • Patent number: 11973466
    Abstract: The present invention is an electronic circuit used to increase voltage levels of electrical signals from sources having low voltage levels for any required application in an electrical system. While the focus is to increase voltage levels, current levels can also be optimized per application requirements. It is built by electronically cascading a clamper circuit or a part of clamper circuit to an oscillator circuit. The oscillator circuit generates an AC signal. The basic functionality of a clamper circuit is to raise DC level of an AC signal. With an oscillator circuit feeding an AC signal to the clamper circuit, multiple applications can be achieved economically. Said invention can be used for driving LEDs at low voltage levels, charge a capacitors to higher voltage levels than a voltage applied to it, low frequency signal amplifiers, low frequency signal generators, AM/FM modulators, etc.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: April 30, 2024
    Inventor: Swaresh Borse
  • Patent number: 11962301
    Abstract: Technologies for low jitter and low power ring oscillators with multi-phase signal reassembly are described. A ring oscillator circuit includes a ring oscillator with a set of M delay stages, each stage outputs a phase signal, where M is a positive integer greater than one. The ring oscillator circuit includes a phase selector circuit coupled to the ring oscillator. The phase selector circuit can receive M phase signals from the ring oscillator and generate N phase signals based on the M phase signals, where N is a positive integer less than M.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Nvidia Corporation
    Inventors: Chun-Ju Shen, Chien-Heng Wong, Ying Wei
  • Patent number: 11960247
    Abstract: According to some aspects of the present disclosure, an atomic clock and methods of forming and/or using an atomic clock are disclosed. In one embodiment, an atomic clock includes: a light source configured to illuminate a resonance vapor cell; a narrowband optical filter disposed between the light source and the resonance vapor cell and arranged such that light emitted from the light source passes through the narrowband optical filter and illuminates the resonance vapor cell. The resonance vapor cell is configured to emit a signal corresponding to a hyperfine transition frequency in response to illumination from the light source, and a filter cell is disposed between the light source and the resonance vapor cell and configured to generate optical pumping. An optical detector is configured to detect the emitted signal corresponding to the hyperfine transition frequency.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: April 16, 2024
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Svenja Knappe, Sean Krzyzewski
  • Patent number: 11953676
    Abstract: A method of synchronizing a first oscillation about a first axis with a second oscillation about a second axis includes: generating a first position signal that indicates a position of the first oscillation about the first axis; generating a second position signal that indicates a position of the second oscillation about the first axis; determining a phase difference between the first and the second position signals; comparing the phase difference to a threshold value to generate a comparison result; generating a first reference signal having a first frequency and a second reference signal having a second frequency; synchronizing the first oscillation to the first frequency and synchronizing the second oscillation to the second frequency; monitoring the comparison result; and synchronously triggering a start of the first reference signal and the second reference signal responsive to the comparison result indicating that the phase difference is less than the threshold value.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: April 9, 2024
    Assignee: Infineon Technologies AG
    Inventors: Norbert Druml, Alberto Garcia Izquierdo
  • Patent number: 11955930
    Abstract: This disclosure relates to multi-phase oscillators for electronic systems. An example system includes multiple level translator circuits and a ring oscillator circuit that includes multiple outputs. Each level translator circuit includes a first input transistor, a second input transistor, and an output. The ring oscillator circuit includes multiple outputs, and each output of the ring oscillator has a different phase. An output of the ring oscillator is coupled to only one input transistor of a level translator circuit, and the other input transistor of the level translator circuit is coupled to an output of another level translator circuit.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: April 9, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Eric A. Sagen, Dheemanth Prabhu Hejamady
  • Patent number: 11949346
    Abstract: The present disclosure relates to an inverter apparatus, a control module of the inverter apparatus, and control methods thereof, and more particularly, to an inverter apparatus enabling stable voltage control using active damping, a control module of the inverter apparatus, and control methods thereof.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: April 2, 2024
    Assignee: HL MANDO CORPORATION
    Inventor: Bong Yeon Choi
  • Patent number: 11949380
    Abstract: A method of manufacturing an oscillator including housing a first resonator and a first integrated circuit device configured to oscillate the first resonator in a first container to manufacture the first oscillator, and housing a second resonator and a second integrated circuit device configured to oscillate the second resonator in a second container to manufacture the second oscillator, wherein the first integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator to output a first oscillation signal, and no PLL circuit, the second integrated circuit device includes a second oscillation circuit configured to oscillate the second resonator to output a second oscillation signal, and a PLL circuit to which the second oscillation signal is input, and which is configured to output a third oscillation signal, and the first container and the second container are containers same in type.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 2, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Naoki Il, Yosuke Itasaka
  • Patent number: 11942929
    Abstract: Methods and devices to control PCM switches are disclosed. The described devices include PCM switch drivers and logic and control circuits, all integrated with the PCM and the associated heater on the same chip. Various architectures for the driver are also presented, including architectures implement feedback mechanism to mitigate variations from process, temperature, and supply voltage.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: PSEMI CORPORATION
    Inventors: Jeffrey A. Dykstra, Jaroslaw Adamski, Edward Nicholas Comfoltey