Abstract: A Floquet mode traveling wave parametric amplifier (TWPA) is disclosed. The Floquet mode TWPA comprises a plurality of stages, where each stage is made up of a nonlinear element and a shunt capacitor. The nonlinear elements may be Josephson junctions, or a combination of series and/or parallel Josephson junctions. The Floquet mode TWPA is designed such that the critical current of the nonlinear elements in each stage is not constant. In some embodiments, the ratio of the largest critical current to the smallest critical current in the Floquet mode TWPA is at least 2:1. In some embodiments, the nonlinear elements with the largest critical current are disposed at or near the input or output of the amplifier. In this way, reflections and backward amplification may be minimized. Further, the TWPA is formed using planar capacitors on a high resistivity substrate, or using low loss parallel plate capacitors.

Abstract: The present invention provides a calibration method of a transmitter, wherein the transmitter includes a power amplifier, a transformer, an adjusting circuit and a coupling circuit, wherein the power amplifier receives an input signal to generate an amplified input signal, the transformer receives the amplified input signal to generate an output signal, the adjusting circuit adjusts phase and amplitude of a common mode signal of the amplified input signal to generate a first signal, and the coupling circuit generates a coupled signal to the output signal according to the first signal. In addition, the calibration method includes: controlling the adjusting circuit to have a specific setting of the phase and amplitude adjustment for the common mode signal, to effectively eliminate a second harmonic generated due to the power amplifier, to improve electromagnetic interference and signal quality.

Abstract: A circuit unit includes a first terminal functioning as a power supply terminal or a voltage input terminal, to which a first voltage is applied, a second terminal to which a second voltage is applied, an oscillation circuit oscillating a vibrator, a first switch electrically coupling or decoupling the first terminal and the oscillation circuit, a second switch electrically coupling or decoupling the second terminal and the oscillation circuit, and a selection circuit controlling the first switch and the second switch based on the first voltage and supplying one of the first voltage and the second voltage as a power supply voltage to the oscillation circuit.

Abstract: Multiple LC parallel resonators in which inductors and capacitors are connected in parallel are located inside a multilayer body. The inductors each include a loop inductor including a line-shaped conductor pattern and at least one pair of via conductors connected to the line-shaped conductor pattern. When the multilayer body is seen through in a height direction, in all the loop inductors of the LC parallel resonators, open via conductors are closer to a center of the multilayer body, and short-circuit via conductors are closer to an outer side of the multilayer body in at least one of a width direction and a length direction.

Abstract: A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.

Abstract: Low temperature coefficient capacitors are described. In an embodiment, a capacitor includes several metal-oxide-semiconductor (MOS) transistors, where each of the several MOS transistors includes a gate, a source and a drain terminal, and where the source and drain terminals of each of the several MOS transistors are connected; several switches, where each of the switches includes two terminals; where first terminals of each of the switches from the several switches are connected together; and where a second terminal of each of the switches from the several switches is connected to a gate terminal of each of the several MOS transistors.

Abstract: An electronic block includes multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL has an input path and an output path. The switch matrix is operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL. In an embodiment, each of the respective signals on the output paths is a corresponding frequency-correction signal generated by a low-pass filter (LPF) in the corresponding PLL. In an embodiment, each PLL includes a frequency-correction signal combiner to combine the frequency-correction signals received from any of the other PLLs with its own frequency-correction signal to form a combined frequency-correction signal. The combined frequency-correction signal is provided to a controlled oscillator in the PLL to generate an output clock of the PLL based on the combined frequency-correction signal. The frequency-correction signals may be analog or digital signals.

Abstract: A power inverter, such as a synchronous buck power inverter, that is configured with a high frequency switching control having a (PWM) controller and sensing circuit. Controller provides a low frequency oscillating wave to effect switching control on a synchronous-buck circuit portion that includes a plurality of switches to invert every half cycle of the frequency provided by controller. The inverting process thus creates a positive and negative transition of the oscillating wave signal. A low frequency switching stage includes a further plurality of switches configured to operate as zero voltage switching (ZVS) and zero current switching (ZCS) drives Charge on an output capacitor is discharged to zero on every zero crossing of low frequency switching stage and advantageously discharges energy every half cycle. During this discharge of energy, the zero crossing distortion in the low frequency sine wave is greatly reduced.

Abstract: A constant-gm current source, arranged to generate a supply current for a Pierce oscillator. First and second transistors have source terminals connected to first and second supply rails, respectively, and drain terminals connected together and to the gate terminal of the first transistor. Third and fourth transistors have source terminals connected to the first and second supply rails, respectively, and drain terminals are connected together and to the gate terminal of the fourth transistor. An output portion varies the supply current in response to a voltage at the drain terminals of the third and fourth transistors. The gate terminals of the first and third transistors are connected together, and the gate terminals of the second and fourth transistors are connected together. An auto-calibration transistor has its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor.

Abstract: Methods, systems, and apparatus for producing CCZ states and T states. In one aspect, a method for transforming a CCZ state into three T states includes obtaining a first target qubit, a second target qubit and a third target qubit in a CCZ state; performing a X?1/2 gate on the third target qubit; performing an X gate on the first target qubit and the second target qubit using the third target qubit as a control; performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control; performing a Z?1/4 gate on the third target qubit; and performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control to obtain the three T states.

Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

Abstract: An oscillator includes a resonator, sustaining circuit and detector circuit. The sustaining circuit receives a sense signal indicative of mechanically resonant motion of the resonator generates an amplified output signal in response. The detector circuit asserts, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation with respect to the sustaining amplifier circuit.

Abstract: A modular sensor system comprising a plurality of modules, the plurality of modules comprising one or more sensors, one or more energy harvesters, one or more energy storage devices, one or more wireless radios, and one or more electronics devices, wherein the one or more energy harvesters comprise a photovoltaic cell; and one or more blind-mate connectors contained within each of the plurality of modules, wherein the one or more blind-mate connectors comprise an electrical connector to transmit power and/or data and configured to connect two modules of the plurality of modules together.

Abstract: An oscillator includes a resonator element, an oscillation circuit configured to oscillate the resonator element to generate a clock signal, a temperature sensor, a digital control circuit configured to operate based on the clock signal and output a control signal based on a temperature detected by the temperature sensor, a temperature control circuit configured to output a control voltage based on the control signal, a temperature control element configured to control a temperature of the resonator element based on the control voltage, and a clock signal abnormality detection circuit configured to detect an abnormality in the clock signal. The clock signal abnormality detection circuit stops an output of the control voltage to the temperature control element performed by the temperature control circuit when the abnormality in the clock signal is detected.

Abstract: An element includes a coupling line in which a first conductor layer, a dielectric layer, and a second conductor layer are stacked in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave; and a bias line connecting a power supply for supplying a bias signal to a semiconductor layer and the second conductor layer. A wiring layer in which the coupling line is formed and a wiring layer in which the bias line is formed are different layers. The bias line is disposed in a layer between the first conductor layer and the second conductor layer.

Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·?f, where M is an integer from 0 to N?1, where N is a number of intervals into which a frequency range for the output signal is divided, and where ?f is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.

Abstract: In an aspect, an apparatus is disclosed that includes a surface-mounted integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving the surface-mounted integrated circuit package, the integrated ceramic resonator including a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate, a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from contact with the conductive periphery of the ceramic cavity, a first conductive material extending vertically through the upper planar surface of the ceramic substrate for connecting the conductive periphery of the ceramic cavity to the surface-mounted integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate for connecting the conductive rod to the surface-mounte

Abstract: The disclosure is directed to characterizing a quantum logic circuit (QLC), via a set of intrinsic parameters. One method includes selecting control vectors that are associated with phase shifts for the intrinsic parameters such that experimental unitary operators for the QLC are defined. Each experimental unitary operator is based on the intrinsic parameters and phase shifts associated with a corresponding control vector. For each control vector, eigenvalues for the corresponding unitary operator are estimated based on qubit measurements performed subsequent to tuning the QLC in accordance with the control vector. The eigenvalues correspond to quasienergy levels of the qubits. Values for the set of intrinsic parameters may be determined based on the eigenvalues.

Abstract: An oscillator acceleration circuit, configured to accelerate the start-up of an oscillator, wherein the oscillator has an input terminal and an output terminal. The oscillator acceleration circuit includes an inverting amplifier, a feedback resistor and an acceleration circuit; the inverting amplifier has an input terminal and an output terminal correspondingly coupled to the input terminal and the output terminal of the oscillator. The feedback resistor is coupled between the input terminal and the output terminal of the oscillator, and the acceleration circuit is coupled between the input terminal and the output terminal of the oscillator. The acceleration circuit is configured to provide a transfer function, wherein the transfer function is the same as the transfer function provided by a resistor and a capacitor connected in parallel; wherein the resistance of the resistor is less than zero.

Abstract: Embodiments disclosed herein relate to oscillators including methods of operating the same, for example for use in radio frequency circuits. In an embodiment, an oscillator has cross-coupled transistors connected between a resonant circuit and a tail circuit. The resonant circuit and tail circuit have respective supply connections for powering the oscillator with an external power supply and the cross-coupled transistors have a bias circuit coupled to respective gates of the cross-coupled transistors and arranged to bias said transistors in an active region of operation. The tail circuit has a current source, a tail capacitor and a tail resistor coupled between a common node of the cross-coupled transistors and the supply connection of the tail circuit.