Abstract: A power supply device converts power supplied from a power source to power to be supplied to a load and supplies the converted power to the load from an output terminal. The power supply device includes a capacitor that includes a case, a first terminal exposed outside the case, and a second terminal exposed outside the case. The first terminal is fixed to a busbar. The busbar electrically connects the first terminal to the output terminal of the power supply device. The second terminal is fixed to an electrically conductive support that receives a reference potential.

Abstract: A dielectric ceramic that includes multiple crystal grains, each of the multiple crystal grains having an interface, a barium titanate (BaTiO3)-based compound as a main component thereof, and a rare earth element. The dielectric ceramic has a cross-section in which the multiple crystal grains has a concentration varying region, a high concentration region, and a low concentration region. The concentration varying region has an RE/Ti ratio differing by 3% or more. The high concentration region has an RE/Ti ratio of 5% to 20%. The low concentration region has an RE/Ti ratio of 0% to 2%.

Abstract: An electronic component according to an embodiment includes a multilayer capacitor, a frame terminal, and a conductive bonding portion. An area in which the conductive bonding portion contacts the frame terminal is larger than an area in which it contacts with the external electrode.

Abstract: A solid electrolytic capacitor element includes an anode body, a dielectric layer formed at the surface of the anode body, and a cathode portion that covers at least a part of the dielectric layer. The cathode portion includes a solid electrolyte layer that covers at least a part of the dielectric layer. The solid electrolyte included in the solid electrolyte layer has a weight reduction ratio of 3% or less when measured through thermogravimetric analysis in which the solid electrolyte is heated to 180° C., is kept at 180° C. for 20 minutes, is cooled from 180° C. to 30° C., and is then heated from 30° C. to 260° C. at a rate of 20° C./min.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including dielectric layers and first internal electrodes and second internal electrodes disposed to face each other and alternately stacked with the respective dielectric layers interposed therebetween; a first external electrode connected to the first internal electrodes; a second external electrode connected to the second internal electrodes; and a protective layer disposed on the ceramic body, the first external electrode, and the second external electrode, wherein the protective layer includes an adhesion assisting layer and a coating layer, an average thickness of the protective layer is 70 nm or more and/or less than 400 nm, and a ratio of an average thickness of the coating layer to the average thickness of the protective layer is 0.25 or more and/or 0.75 or less.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer having a main component represented by (Ba1-xCax)(Ti1-y (Zr, Hf)y)O3 (where, 0?x?1, 0?y?0.5), and including first and second internal electrodes alternately stacked with the dielectric layer interposed therebetween; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode, wherein at least one of the dielectric layer and the internal electrode includes Sn or Dy. If Sn, an average content of Sn at an interface between the dielectric layer and the internal electrode is within a range of 5 at % or more and 20 at % or less. If Dy, an average content of Dy at an interface between the dielectric layer and the internal electrode is within a range of 1 at % or more and 5 at % or less.

Abstract: A multilayer electronic component includes: a body including a capacitance forming portion in which dielectric layers and internal electrodes are alternately disposed in a first direction, and cover portions disposed on an upper surface and a lower surface of the capacitance forming portion, respectively, in the first direction; and external electrodes disposed on the body, wherein the cover portion includes a plurality of dielectric grains and a plurality of pores, and Gn/Pn is more than 10 and less than 30, in which Gn is the number of dielectric grains included in the cover portion and Pn is the number of pores included in the cover portion.

Abstract: A multilayer ceramic capacitor includes a multilayer body in which dielectric layers are laminated, first and second internal electrode layers extending to both end surfaces of the multilayer body, first and second external electrodes connected to the first internal electrode layer and disposed on both end surfaces, and third and fourth external electrodes connected to the second internal electrode layer and disposed on both side surfaces. A number of the first internal electrode layers is greater than a number of the second internal electrode layers, and at least two first internal electrode layers are continuously laminated. In the first internal electrode layer, a recess is provided so as not to overlap the third and fourth external electrodes on a portion of both principal surfaces when the multilayer ceramic capacitor is viewed from a height direction.

Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.

Abstract: A film capacitor that includes a capacitor element including one or more wound or laminated metallized films, each metallized film including a dielectric resin film and a metal layer on one surface of the dielectric resin film; a cover covering an outer surface of the capacitor element in a direction in which layers of the dielectric resin film are laminated with the metal layer therebetween; and an exterior body covering an outer periphery of the capacitor element and an outer surface of the cover. In a first aspect, the dielectric resin film contains a curable resin as a main component thereof, and the cover is made of a thermoplastic resin.

Abstract: A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween and including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction.

Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a capacitor portion and a substrate body portion. The capacitor portion includes a plurality of wall portions having a lengthwise direction and separated from each other by a trench formed on a first main surface of the substrate. The substrate body portion is formed around the capacitor portion using a portion of the substrate. The plurality of wall portions are formed of a plurality of pillar units. The capacitor portion, in the plan view, includes a first capacitor portion and a second capacitor portion. The first capacitor portion includes the plurality of wall portions having the lengthwise direction as a first lengthwise direction. The second capacitor portion includes the plurality of wall portions having the lengthwise direction as a second lengthwise direction orthogonal to the first lengthwise direction.

Abstract: A multilayer electronic component includes: a body including dielectric layers and internal electrodes alternately disposed with the dielectric layers interposed therebetween in a first direction; and external electrodes connected to the internal electrodes. The body has first and second surfaces opposing each other in the first direction and one or more side surfaces positioned between the first and second surfaces. The body has a protruding portion protruding in the first direction and outer peripheral portions around the protruding portion on the first surface of the body. The external electrodes cover the outer peripheral portions, the side surfaces, and the second surface of the body. In the second surface of the body, portions that are covered by the external electrodes and a portion that is not covered by the external electrodes are substantially coplanar with each other.

Abstract: There are provided a dielectric composition and a multilayer capacitor including the same. The dielectric composition contains: barium titanate (BaTiO3); and 0.6 to 0.9 mol of calcium (Ca) and 0.5 to 2.0 mol of magnesium (Mg) based on 100 mol of barium titanate.

Abstract: A ceramic electronic component includes a multilayer structure having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, the dielectric layers being mainly composed of ceramic, the internal electrode layers being formed so as to be alternately exposed to two edge faces opposite to each other of the multilayer structure, and cover layers respectively disposed on top and bottom faces of the multilayer structure in a stack direction, the cover layers being mainly composed of ceramic, wherein at least one of a Sn concentration with respect to a main component ceramic in the cover layer or a Sn concentration with respect to a main component ceramic in a side margin section is higher than a Sn concentration with respect to a main component ceramic in a capacity section.

Abstract: A multilayer capacitor includes a capacitor body having an active region, upper and lower cover regions, and width margins on opposing sides of the active region. The width margin includes a first region on an internal side thereof adjacent the first and second internal electrodes and a second region on an external side between the first region and a respective external surface of the capacitor body, and the upper and lower cover regions each include a third region on an internal side thereof adjacent the internal electrodes and a fourth region on an external side between the third region and a respective external surface of the capacitor body. The active region, the second region, and the fourth region have a same dielectric constant A, and the first and third regions have a same dielectric constant B, and A and B are different from each other and satisfy 0.5?B/A.

Abstract: A capacitor header for coupling a voltage output from a capacitor, which allows the capacitor to store a large amount of charge and then discharge this as a high voltage, while reducing the risk of dielectric breakdown. The capacitor header includes a live output plate connected to a central live conductor of the capacitor and a ground output plate connected to a ground conductor of the capacitor. The capacitor header also includes first and second insulating members, which both have non-planar mating surfaces that interleave to form a non-linear path. An insulating seal is included between the non-planar mating surfaces. The capacitor header also includes two sets of insulating sheets. The sets of insulating sheets extend beyond an outer perimeter of the live output plate and the ground output plate.

Abstract: A multilayer ceramic capacitor includes a multilayer body including ceramic layers, internal electrodes and a pair of side surfaces, and side margin portions, wherein each of ceramic layers and the side margin portions is composed of a polycrystalline body having a perovskite structure, wherein the side margin portions contain at least one of calcium and strontium, when the side margin portions contain calcium, an atomic ratio of the calcium to titanium in the side margin portions is greater than that in the ceramic layers, and when the side margin portions contains strontium, the atomic ratio of the strontium to titanium in the side margin portions is greater than that in the ceramic layers, wherein glass particles composed of silicon as a main component are dispersed in the polycrystalline body, and an atomic ratio of silicon to titanium is 1 at % or more and 10 at % or less.

Abstract: A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrodes each at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface in a lamination direction of the capacitor main body, and opposed and spaced apart from each other in a length direction connecting the two end surfaces. The two interposers each include a first recess portion on an end surface of the interposer opposed to an end surface facing the other interposer, in an area around a middle portion of the interposer in a width direction, and second recess portions on both sides in the width direction of the first recess portion, and each having a thickness of about ±10% of a half of a thickness of the interposer.