Patents Examined by Asok K. Sarkar
  • Patent number: 11963382
    Abstract: Provided are a display substrate and a preparation method thereof, and a display device. A display region and a binding region located at one side of the display region are comprised. The display region comprises a driving structure layer, an organic insulating layer disposed on the driving structure layer and a light-emitting element disposed on the organic insulating layer, the driving structure layer comprises a pixel driving circuit, and the light-emitting element is connected with the pixel driving circuit. The binding region comprises a binding structure layer, an organic insulating layer and an isolation dam disposed on the binding structure layer, and an inorganic encapsulation layer disposed on the organic insulating layer and the isolation dam, the binding structure layer comprises a power line connected with the pixel driving circuit; at least one isolation groove is disposed on the organic insulating layer of the binding region.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 16, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Pengfei Yu, Chenxing Wan
  • Patent number: 11955563
    Abstract: The present disclosure provides a thin film transistor, a manufacturing method of the thin film transistor, and a liquid crystal display. The thin film transistor includes a substrate; an active region arranged above the substrate; a channel region arranged in a center of the active region; source and drain regions arranged on two sides of the channel region; a gate dielectric layer arranged above the channel region; a reflective coating arranged above the gate dielectric layer; a gate metal arranged above the reflective coating; an interlayer dielectric layer covering the gate metal, the active region, and the substrate; and a source/drain metal layer passing through the interlayer dielectric layer and electrically connecting with a surface of the source and drain regions.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 9, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Mingjuan Li
  • Patent number: 11948834
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11935740
    Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: March 19, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Francis Arendt, Damien Thomas Gilmore
  • Patent number: 11923191
    Abstract: A substrate processing technique including: (a) modifying a first base surface of a substrate by supplying a first modifier and a second modifier to the substrate having a surface on which the first base and a second base are exposed, wherein the first modifier contains one or more atoms to which at least one first functional group and at least one second functional group are directly bonded, wherein the second modifier contains an atom to which at least one first functional group and at least one second functional group are directly bonded, and wherein the number of the at least one first functional group contained in one molecule of the second modifier is smaller than the number of the at least one first functional group contained in one molecule of the first modifier; and (b) forming a film on a second base surface by supplying film-forming gas to the substrate.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: March 5, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Shoma Miyata, Kimihiko Nakatani, Takayuki Waseda, Takashi Nakagawa, Motomu Degai
  • Patent number: 11915974
    Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Shuangqiang Luo, Alyssa N. Scarbrough
  • Patent number: 11911842
    Abstract: A crystalline material processing method includes forming subsurface laser damage at a first average depth position to form cracks in the substrate interior propagating outward from at least one subsurface laser damage pattern, followed by imaging the substrate top surface, analyzing the image to identify a condition indicative of presence of uncracked regions within the substrate, and taking one or more actions responsive to the analyzing. One potential action includes changing an instruction set for producing subsequent laser damage formation (at second or subsequent average depth positions), without necessarily forming additional damage at the first depth position. Another potential action includes forming additional subsurface laser damage at the first depth position.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 27, 2024
    Assignee: WOLFSPEED, INC.
    Inventors: Matthew Donofrio, John Edmond, Harshad Golakia, Eric Mayer
  • Patent number: 11908684
    Abstract: Methods of and systems for reforming films comprising silicon nitride are disclosed. Exemplary methods include providing a substrate within a reaction chamber, forming activated species by irradiating a reforming gas with microwave radiation, and exposing substrate to the activated species. A pressure within the reaction chamber during the step of forming activated species can be less than 50 Pa.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: February 20, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Shinya Yoshimoto, Jun Yoshikawa, Toshihisa Nozawa
  • Patent number: 11908896
    Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jiefeng Lin, Jeng-Ya Yeh, Chih-Yung Lin
  • Patent number: 11908683
    Abstract: The present application discloses a manufacturing method of a silicon nitride thin film, a thin film transistor and a display panel, the method includes following steps: providing a silane precursor into an atomic layer deposition apparatus for a preset time period, and remaining the silane precursor for a preset time period after the provision; providing an inert gas into the atomic layer deposition apparatus for a preset time period for the first time, and purging the silane precursor; providing a nitrogen supplying precursor into the atomic layer deposition apparatus for a preset time period, and remaining the nitrogen supplying precursor for a preset time period after the provision; providing the inert gas into the atomic layer deposition apparatus for a preset time period for the second time, and purging the nitrogen supplying precursor; repeating for a preset number of times the steps of providing the silane precursor, providing the inert gas for the first time, providing the nitrogen supplying precurso
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 20, 2024
    Assignees: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: En-Tsung Cho, Wanfei Yong, Je-Hao Hsu, Yuming Xia, Haijiang Yuan
  • Patent number: 11901435
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated circuit (IC). The method includes forming a gate electrode and a gate dielectric stacked over a substrate. A sidewall liner is formed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer is formed on sidewalls and an upper surface of the sidewall liner. The sidewall spacer consists essentially of silicon oxycarbonitride and has a dielectric constant great than that of the sidewall liner and less than that of the gate dielectric. A pair of source/drain regions is formed respectively on opposite sides of the gate electrode.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng-Ta Wu
  • Patent number: 11901175
    Abstract: A method for selectively depositing silicon nitride on a first material relative to a second material is disclosed. An exemplary method includes treating the first material, and then selectively depositing a layer comprising silicon nitride on the second material relative to the first material. Exemplary methods can further include treating the deposited silicon nitride.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 13, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Eric James Shero, Paul Ma, Bed Prasad Sharma, Shankar Swaminathan
  • Patent number: 11901158
    Abstract: A plasma processing method includes providing a plasma processing apparatus including a rotary table that is rotatably provided in a vacuum container and disposes a plurality of substrates on an upper surface along a circumferential direction, a gas supply source that supplies a plasma processing gas to at least one of a plurality of processing areas separated by a separation area in the circumferential direction of the rotary table, and an antenna that is provided to face the upper surface of the rotary table and generates plasma in the at least one processing area. The plasma processing method further includes disposing the plurality of substrates on the rotary table, and supplying the plasma processing gas into the vacuum container and supplying a pulsed wave of RF power to the antenna while rotating the rotary table.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: February 13, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takeshi Kobayashi, Hiroyuki Kikuchi
  • Patent number: 11894261
    Abstract: A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV?1 to 1.2*1010 cm2 eV?1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 6, 2024
    Inventor: Addison Crockett
  • Patent number: 11885016
    Abstract: There is included (a) forming a film on a substrate by supplying a first processing gas to the substrate in a process container; (b) forming a first pre-coated film, which has a first thickness and has a material different from a material of the film formed in (a), in the process container by supplying a second processing gas into the process container in a state in which the substrate does not exist in the process container; and (c) forming a second pre-coated film, which has a second thickness smaller than the first thickness and has the same material as the material of the film formed in (a), on the first pre-coated film formed in the process container by supplying a third processing gas into the process container in the state in which the substrate does not exist in the process container.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 30, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kazuhiro Harada, Shintaro Kogura, Masayoshi Minami
  • Patent number: 11877453
    Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, a plurality of channel holes penetrating the alternating layer stack, a channel structure in each channel hole, and a top selective gate cut structure having a laminated structure and located between two rows of channel structures.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 16, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kun Zhang
  • Patent number: 11871567
    Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, and a top selective gate cut structure having a laminated structure embedded in an upper portion of the alternating layer stack and extending along a lateral direction. The laminated structure of the top selective gate cut structure comprises a dielectric filling wall and a dummy channel and a dummy functional layer on both sides of the dielectric filling wall.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: January 9, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kun Zhang
  • Patent number: 11862510
    Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; for a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventor: Mie Matsuo
  • Patent number: 11855189
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Patent number: 11855095
    Abstract: A semiconductor device includes a semiconductor substrate and a first dielectric layer. The semiconductor substrate includes at least one fin. The first dielectric layer is disposed on the at least one fin. A thickness of the first dielectric layer located on a top surface of the at least one fin is greater than a thickness of the first dielectric layer located on a sidewall of the at least one fin.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-I Lin, Chun-Heng Chen, Ming-Ho Lin, Chi-On Chui