Patents Examined by Asok K. Sarkar
  • Patent number: 12382633
    Abstract: A microelectronic device includes tiers of alternating dielectric and conductive materials, a cap oxide material vertically adjacent to the tiers, and pillars extending vertically through the tiers. The cap oxide material is formulated to exhibit a different etch rate relative to an etch rate of the oxide material of the tiers. Additional microelectronic devices, microelectronic systems, and methods of forming a microelectronic device are also disclosed.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: August 5, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Frank Speetjens, Yucheng Wang, Brendan Flynn, S M Istiaque Hossain, Tom J. John, Jeremy Adams
  • Patent number: 12382756
    Abstract: A micro light-emitting element includes a first conductivity type semiconductor layer including a lower surface on which an uneven pattern is formed, an active layer provided on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer provided on the active layer, at least one electrode provided on the second conductivity type semiconductor layer, and a transparent coating layer including a first surface covering the lower surface of the first conductivity type semiconductor layer, and a second surface facing the first surface and having a second surface roughness that is less than a first surface roughness of the lower surface of the first conductivity type semiconductor layer.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: August 5, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunjoon Kim, Dongkyun Kim, Dongho Kim, Joonyong Park, Seogwoo Hong, Kyungwook Hwang, Junsik Hwang
  • Patent number: 12381077
    Abstract: A method of filling a recess on a surface of a substrate may comprise performing a deposition cycle on the substrate; allowing the deposited material to flow into the recess; and creating a void within the recess in response to the allowing the deposited material to flow. A void size of the void can be based on a ratio of a deposition repeat number of times that the deposition step is repeated to a treatment repeat number of times that the treatment cycle is repeated. The deposition cycle can comprise: providing an inert gas to the reaction chamber; performing a deposition step; and performing a treatment step. A deposition step can comprise: providing a precursor to the reaction chamber; and/or forming a deposited material from the precursor. A treatment step can comprise forming a plasma in the reaction chamber by applying a plasma power and treating the deposited material.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: August 5, 2025
    Assignee: ASM IP Holding B.V.
    Inventor: Jungtak Seo
  • Patent number: 12381076
    Abstract: An inherently selective process for the deposition of silicon-containing dielectric layers on metal layers includes atomic layer deposition or chemical vapor deposition utilizing a chemical precursor comprising silicon and sulfur, and an oxidant. An optional buffer layer may be present between the metal layer and the selectively deposited film.
    Type: Grant
    Filed: August 1, 2024
    Date of Patent: August 5, 2025
    Assignee: GELEST, INC.
    Inventors: Chad Michael Brick, Tomoyuki Ogata
  • Patent number: 12374544
    Abstract: A substrate processing technique including: (a) modifying a first base surface of a substrate by supplying a first modifier and a second modifier to the substrate having a surface on which the first base and a second base are exposed, wherein the first modifier contains one or more atoms to which at least one first functional group and at least one second functional group are directly bonded, wherein the second modifier contains an atom to which at least one first functional group and at least one second functional group are directly bonded, and wherein the number of the at least one first functional group contained in one molecule of the second modifier is smaller than the number of the at least one first functional group contained in one molecule of the first modifier; and (b) forming a film on a second base surface by supplying film-forming gas to the substrate.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: July 29, 2025
    Assignee: Kokusai Electric Corporation
    Inventors: Shoma Miyata, Kimihiko Nakatani, Takayuki Waseda, Takashi Nakagawa, Motomu Degai
  • Patent number: 12376316
    Abstract: A semiconductor device including at least one memory cell is provided. The memory cell includes: a first electrode layer; a second electrode layer; a selection element layer coupled between the first electrode layer and the second electrode layer; and an insulating layer coupled between the first electrode layer and the second electrode such that a side surface of the insulating layer is in contact with a side surface of the selection element layer, wherein the selection element layer includes an insulating material doped with a first element, and wherein the insulating layer includes the insulating material doped with the first element at a lower concentration than the selection element layer, or the insulating material not doped with the first element.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: July 29, 2025
    Assignee: SK HYNIX INC.
    Inventor: Jeong Hwan Song
  • Patent number: 12374581
    Abstract: A method includes manufacturing a plurality of wafers each having a substrate having an active surface and a backside, and a stop layer dividing the substrate into a first substrate part at a side of the active surface and a second substrate part at a side of the backside; on a first wafer of the plurality of wafers, removing the second substrate part and the stop layer; bonding a second wafer of the plurality of wafers on the first wafer with first substrate part of the second wafer facing a surface of the first wafer that is exposed by removing the stop layer and, on the second wafer, performing the same processes of removing the second substrate part and stop layer of the second wafer; repeating the bonding and removing the second substrate part and stop layer with one or more wafers to form a stack of wafers.
    Type: Grant
    Filed: September 24, 2024
    Date of Patent: July 29, 2025
    Assignee: Nexthin Technology
    Inventor: Tzu-wei Chiu
  • Patent number: 12356782
    Abstract: A display device includes pixel areas each having an emission area, and a pixel in each of the pixel areas and including a display element part. The display element part includes a first insulating layer on a substrate, a light emitting element on the first insulating layer and each having first and second ends, a first layer on the first insulating layer and the light emitting element and contacting a first area of each of the first and second ends of the light emitting element, a second layer on the light emitting element and contacting a second area of each of the first and second ends of the light emitting element, and an interlayer insulating layer between the first layer and the second layer. The first layer and the second layer include a semiconductor material.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 8, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Min Shin, Sang Woo Kim, Jang Yeol Yoon, Gyung Soon Park
  • Patent number: 12342587
    Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Chien Ning Yao, Shih-Cheng Chen, Jung-Hung Chang, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 12341055
    Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, a control layer disposed over the first ILD layer and containing silicon and oxygen, and a resistor wire disposed over the control layer. An oxygen concentration of the control layer is greater than an oxygen concentration of the first ILD layer.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun-Nan Nian, Yao-Hsiang Liang, Ming-Ching Chung, Hsueh-Han Lu, Chun-Ju Wu
  • Patent number: 12341073
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a forming method of a semiconductor structure and a semiconductor structure. The forming method of a semiconductor structure includes: placing a target structure in a reaction chamber; forming a first oxide layer on the target structure, where the first oxide layer has a first thickness; and forming a second oxide layer under the first oxide layer, where the second oxide layer has a second thickness, and the first thickness is less than the second thickness.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Huiwen Tang
  • Patent number: 12334394
    Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate comprises a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AlO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (H2) or ammonia (NH3) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AlO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: June 17, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Suketu Parikh, Mihaela A. Balseanu, Bhaskar Jyoti Bhuyan, Ning Li, Mark Joseph Saly, Aaron Michael Dangerfield, David Thompson, Abhijit B. Mallick
  • Patent number: 12329019
    Abstract: Provided are a display substrate, a manufacturing method thereof, a display device. The display substrate includes sub-pixel units on a base layer, each sub-pixel unit includes a light propagation unit including a first medium structure and a second medium structure, orthographic projections of the first medium structure and the light emitting unit on the base layer are at least partially overlapped, the second medium structure contacts at least one side of the first medium structure. The first medium structure has a refractive index larger than that of the second medium structure. A first included angle between a diagonal line and a bottom side of a first cross section of the first medium structure is equal to a total reflection angle at a contact surface between the first medium structure and the second medium structure. The first included angle is smaller than or equal to a preset angle.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 10, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhenye Wei, Qiyun Wang, Hongwei Zhang, Li Chen, Cheng Zeng, Xiongyi Luo
  • Patent number: 12322592
    Abstract: A processing method comprises positioning a substrate in a processing chamber and setting a temperature of the substrate to a range of 50° C. to 500° C.; conducting an atomic layer deposition (ALD) cycle on the substrate; and repeating the ALD cycle to form a silicon oxide film. The ALD cycle comprises: exposing the substrate to an aminosilane precursor in the processing chamber by pulsing a flow of the aminosilane precursor; purging the processing chamber of the aminosilane precursor; exposing the substrate to an oxidizing agent by pulsing a flow of the oxidizing agent for a duration in a range of greater than or equal to 100 milliseconds to less than or equal to 3 seconds; and purging the processing chamber of the oxidizing agent.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: June 3, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Geetika Bajaj, Prerna Sonthalia Goradia, Seshadri Ganguli, Srinivas Gandikota, Robert Jan Visser, Suraj Rengarajan
  • Patent number: 12315718
    Abstract: A method includes depositing a flowable film on a substrate by providing a first input flow, the first input flow including plasma effluents of a first precursor, removing a portion of the flowable film from a sidewall of a feature defined within the substrate to obtain a remaining portion of the flowable film by providing a second input flow, the second input flow including plasma effluents of a second precursor, reducing hydrogen content of the remaining portion of the flowable film to obtain a densified film by providing a third input flow, the third input flow including plasma effluents of a third precursor, and treating the densified film in accordance with a film treatment process.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 27, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Bhargav S. Citla, Srinivas D. Nemani, Purvam Modi, Ellie Y. Yieh
  • Patent number: 12293942
    Abstract: Methods and systems for manufacturing a structure comprising a substrate. The substrate comprises plurality of recesses and a plurality of lateral spaces. The recesses and lateral spaces are at least partially filled with a gap filling fluid.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: May 6, 2025
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Blanquart
  • Patent number: 12290835
    Abstract: The present disclosure provides embodiments of processes and methods for stabilizing self-assembled monolayers (SAMs). In the present disclosure, a cyclic vapor deposition process is used to selectively deposit a polymer thin film on a SAM structure formed on a target material. The polymer thin film selectively deposited on the SAM structure stabilizes the SAM structure by: (a) healing defects in the SAM structure and providing blanket coverage over the target material surface, (b) preventing migration of SAM-forming molecules to neighboring non-target surfaces, and (c) increasing the thickness and rigidity of the SAM structure. In one embodiment, sequentially pulsed initiated chemical vapor deposition (spiCVD) is used to selectively deposit the polymer thin film on the SAM structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 6, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Omid Zandi, Jacques Faguet, Ornella Sathoud
  • Patent number: 12279470
    Abstract: An electroluminescent device, a display substrate, and a display apparatus. The electroluminescent device comprises: an electron transport layer (1) and a quantum dot light emitting layer (3) that are arranged in a stack mode; and an ionic complex layer (2) located between the electron transport layer (1) and the quantum dot light emitting layer (3), wherein a built-in electric field is formed in the ionic complex layer (2).
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 15, 2025
    Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.
    Inventor: Dong Li
  • Patent number: 12272608
    Abstract: Methods for reducing warpage of bowed semiconductor substrates, including providing a first substrate to a first station in a semiconductor processing chamber, providing a second substrate to a second station in the semiconductor processing chamber, concurrently depositing a first bow compensation layer of material on the backside of the first substrate at the first station and a first bow compensation layer of material on the backside of the second substrate at the second station, and depositing a second bow compensation layer of material on the backside of the first substrate, while the first substrate is at the first station and the second substrate is at the second station, and while not concurrently depositing material on the backside of the second substrate.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: April 8, 2025
    Assignee: Lam Research Corporation
    Inventors: Yanhui Huang, Vignesh Chandrasekar
  • Patent number: 12272548
    Abstract: Methods of and systems for reforming films comprising silicon nitride are disclosed. Exemplary methods include providing a substrate within a reaction chamber, forming activated species by irradiating a reforming gas with microwave radiation, and exposing substrate to the activated species. A pressure within the reaction chamber during the step of forming activated species can be less than 50 Pa.
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: April 8, 2025
    Assignee: ASM IP Holding B.V.
    Inventors: Shinya Yoshimoto, Jun Yoshikawa, Toshihisa Nozawa