Patents Examined by Asok K. Sarkar
  • Patent number: 11417514
    Abstract: There is provided a film forming method, including: forming a film containing silicon, carbon and nitrogen on a substrate in a first process; and oxidizing the film with an oxidizing agent containing a hydroxy group and subsequently supplying a nitriding gas to the substrate in a second process.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: August 16, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuichiro Wagatsuma, Toyohiro Kamada, Shinichi Ike, Shuji Azumo
  • Patent number: 11417635
    Abstract: Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, a light extraction surface of each substrate portion includes protruding features and light extraction surface recesses. Lateral borders between different pixels are aligned with selected light extraction surface recesses. In some aspects, selected light extraction surface recesses extend through an entire thickness of the substrate. Other technical benefits may additionally or alternatively be achieved.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 16, 2022
    Assignee: CREELED, INC.
    Inventor: Peter Scott Andrews
  • Patent number: 11404268
    Abstract: A method for growing a GaN crystal suitable as a material of GaN substrates including C-plane GaN substrates includes: a first step of preparing a GaN seed having a nitrogen polar surface; a second step of arranging a pattern mask on the nitrogen polar surface of the GaN seed, the pattern mask being provided with a periodical opening pattern comprising linear openings and including intersections, the pattern mask being arranged such that longitudinal directions of at least part of the linear openings are within ±3° from a direction of an intersection line between the nitrogen polar surface and an M-plane; and a third step of ammonothermally growing a GaN crystal through the pattern mask such that a gap is formed between the GaN crystal and the pattern mask.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: August 2, 2022
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yutaka Mikawa, Hideo Fujisawa, Tae Mochizuki, Hideo Namita, Shinichiro Kawabata
  • Patent number: 11398410
    Abstract: A method for manufacturing a CMOS device includes: forming a gate structure and gate sidewalls of the CMOS device, wherein the material of the gate sidewalls is silicon nitride; depositing a silicon nitride film directly on the gate structure and the gate sidewalls, wherein the depositing is performed via atomic layer deposition (ALD); and performing a photolithography process to define an ion implantation region.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: July 26, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventors: Runling Li, Xuefei Chen
  • Patent number: 11393689
    Abstract: A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: July 19, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITE GRENOBLE ALPES
    Inventors: Nicolas Posseme, Marceline Bonvalot, Ahmad Chaker, Christophe Vallee
  • Patent number: 11393678
    Abstract: Methods for deposition of high-hardness low-? dielectric films are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate, the precursor having the general formula (I) wherein R1, R2, R3, R4, R5, R6, R7, and R8 are independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, or halide; maintaining the substrate at a pressure in a range of about 0.1 mTorr and about 10 Torr and at a temperature in a range of about 200° C. to about 500° C.; and generating a plasma at a substrate level to deposit a dielectric film on the substrate.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 19, 2022
    Assignee: Applied Materials, Inc.
    Inventors: William J. Durand, Mark Saly, Lakmal C. Kalutarage, Kang Sub Yim, Shaunak Mukherjee
  • Patent number: 11393673
    Abstract: A deposition method includes a first process performed by repeating causing aminosilane gas to be adsorbed on a substrate; causing a first silicon oxide film to be stacked on the substrate by supplying oxidation gas to the substrate to oxidize the aminosilane gas adsorbed on the substrate; and performing a reforming process on the first silicon oxide film by activating a first reformed gas by plasma and supplying the first reformed gas to the first silicon oxide film, and a second process, performed after the first process, by repeating causing aminosilane gas to be adsorbed on the substrate; causing a second silicon oxide film to be stacked on the substrate by supplying oxidation gas; and performing a reforming process on the second silicon oxide film by supplying a plasma-activated second reformed gas. The first reformed gas has a smaller effect of oxidizing the substrate than the second reformed gas.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: July 19, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Chiba, Jun Sato
  • Patent number: 11387321
    Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiefeng Lin, Jeng-Ya Yeh, Chih-Yung Lin
  • Patent number: 11374114
    Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Patent number: 11371144
    Abstract: Methods for plasma enhanced atomic layer deposition (PEALD) of low-K films are described. A method of depositing a film comprises exposing a substrate to a silicon precursor having the general formula (I) wherein R1, R2, R3, R4, R5, and R6 are independently selected from hydrogen (H), substituted alkyl, or unsubstituted alkyl; purging the processing chamber of the silicon precursor; exposing the substrate to a carbon monoxide (CO) plasma to form one or more of a silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) film on the substrate; and purging the processing chamber.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Shuaidi Zhang, Ning Li, Mihaela Balseanu
  • Patent number: 11362120
    Abstract: A technique comprising: providing an assembly temporarily adhered on opposite sides to respective carriers by respective adhesive elements, the assembly including at least one plastic support sheet; heating the assembly while mechanically compressing the assembly between the carriers, wherein the strength of adhesion of one of said adhesive elements to the respective carrier and/or to the assembly is partially reduced during said heating of the assembly under mechanical compression; and wherein the strength of adhesion of the said adhesive element to the carrier and/or to the assembly is further reducible by further heating the said adhesive element after partially or completely relaxing the pressure at which the assembly is mechanically compressed between the two carriers.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: June 14, 2022
    Assignee: FLEXENBLE LIMITED
    Inventor: Barry Wild
  • Patent number: 11355338
    Abstract: Methods of depositing material on a surface of a substrate are disclosed. The methods include exposing a surface of the substrate to a precursor within a reaction chamber to form adsorbed species on the surface and removing at least a portion of the adsorbed species prior to introducing a reactant to the reaction chamber.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: June 7, 2022
    Assignee: ASM IP Holding B.V.
    Inventor: Shinya Ueda
  • Patent number: 11348782
    Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 31, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Francis Arendt, Damien Thomas Gilmore
  • Patent number: 11342187
    Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 24, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Patent number: 11335554
    Abstract: There is provided a technique that includes: (a) modifying a surface of one base among a first base and a second base to be F-terminated by supplying a fluorine-containing radical generated from a fluorine-containing gas to a substrate where the first base and the second base are exposed at a surface of the substrate; and (b) forming a film on a surface of the other base, which is different from the one base, among the first base and the second base by supplying a film-forming gas to the substrate after modifying the surface of the one base.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 17, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takashi Nakagawa, Takayuki Waseda, Kimihiko Nakatani, Motomu Degai
  • Patent number: 11305986
    Abstract: There is provided a technique for improving a resistance of a film to vibration in a semiconductor device having a vibrating film, including at least: forming a first silicon oxide film; forming a first silicon nitride film; forming a second silicon oxide film; and forming a second silicon nitride film, and each film formation is performed using a substrate processing apparatus configured to supply gas to a process chamber including upper and bottom electrodes, and selectively supply high frequency power or low frequency power to each of the upper and bottom electrodes by switching.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 19, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takashi Yahata, Naofumi Ohashi, Tadashi Takasaki
  • Patent number: 11296209
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated circuit (IC). The method includes forming a gate electrode and a gate dielectric stacked over a substrate. A sidewall spacer layer is deposited over the substrate and the gate electrode, in which the sidewall spacer layer lines sidewalls of the gate electrode. An etching back is performed on the sidewall spacer layer to form a sidewall spacer on the sidewalls of the gate electrode. The etching back is performed at an etch rate less than about 8 angstroms/minute using an etchant comprising hydrogen fluoride. Further, the substrate is doped with the sidewall spacer and the gate electrode in place to form a pair of source/drain regions respectively on opposite sides of the gate electrode.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng-Ta Wu
  • Patent number: 11296084
    Abstract: Provided are a deposition method, a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate and a dielectric structure. The substrate includes at least one fin thereon. The dielectric structure covers the at least one fin. A thickness of the dielectric structure located on a top surface of the at least one fin is greater than a thickness of the dielectric structure located on a sidewall of the at least one fin. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is conformally disposed on the at least one fin. The second dielectric layer is disposed on the first dielectric layer over the top surface of the at least one fin. A thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-I Lin, Chun-Heng Chen, Ming-Ho Lin, Chi-On Chui
  • Patent number: 11282707
    Abstract: A method includes: receiving a first wafer; defining a first zone and a second zone on the first wafer and a plurality of first areas; defining a plurality of first areas and second areas for the first and second zones, respectively; projecting first ion beams onto the first areas and receiving first thermal waves in response to the first ion beams; rotating the first wafer by a twist angle; projecting second ion beams onto the second areas and receiving second thermal waves in response to the second ion beams; and estimating a first crystalline orientation angle of the first wafer based on the first and second ion beams and the first and second thermal waves.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Bo-Tsung Tsai
  • Patent number: 11282698
    Abstract: A method of forming a topology-controlled layer on a patterned recess of a substrate, includes: (i) depositing a Si-free C-containing film having filling capability on the patterned recess of the substrate by pulse plasma-assisted deposition to fill the recess in a bottom-up manner or bottomless manner; and (ii) subjecting the bottom-up or bottomless film filled in the recess to plasma aching to remove a top portion of the filled film in a manner leaving primarily or substantially only a bottom portion of the filled film or primarily or substantially only a sidewall portion of the filled film.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: March 22, 2022
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart