Abstract: Methods of and systems for reforming films comprising silicon nitride are disclosed. Exemplary methods include providing a substrate within a reaction chamber, forming activated species by irradiating a reforming gas with microwave radiation, and exposing substrate to the activated species. A pressure within the reaction chamber during the step of forming activated species can be less than 50 Pa.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, including providing a first substrate to a first station in a semiconductor processing chamber, providing a second substrate to a second station in the semiconductor processing chamber, concurrently depositing a first bow compensation layer of material on the backside of the first substrate at the first station and a first bow compensation layer of material on the backside of the second substrate at the second station, and depositing a second bow compensation layer of material on the backside of the first substrate, while the first substrate is at the first station and the second substrate is at the second station, and while not concurrently depositing material on the backside of the second substrate.

Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material.

Abstract: A method for manufacturing a mirror device, the method includes a first step of preparing a wafer having a support layer, a device layer, and an intermediate layer; a second step of forming a slit in the wafer such that the movable portion becomes movable with respect to the base portion by removing a part of each of the support layer, the device layer, and the intermediate layer from the wafer and forming a plurality of parts each corresponding to the structure in the wafer, after the first step; a third step of performing wet cleaning using a cleaning liquid after the second step; and a fourth step of cutting out each of the plurality of parts from the wafer after the third step. In the second step, a part of the intermediate layer is removed from the wafer by anisotropic etching.

Abstract: A semiconductor light emitting device includes a package body including a concave portion surrounded by sidewalls, a light emitting diode (LED) chip on a mounting surface of the concave portion, a lead frame in the package body and electrically connected to the LED chip, a wavelength conversion layer in the concave portion and surrounding the LED chip, the wavelength conversion layer being surrounded by the sidewalls of the package body and including a wavelength conversion material, and a transparent resin layer on the wavelength conversion layer, the transparent resin layer having first opposite side surfaces exposed through sides of the package body and spaced apart from each other along a first direction parallel to the mounting surface, and second opposite side surfaces contacting an inner surface of the package body and spaced apart from each other in a second direction parallel to the mounting surface.

Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer above the substrate; a high-resistance layer above the nitride semiconductor layer; a p-type nitride semiconductor layer above the high-resistance layer; a first opening penetrating through the p-type nitride semiconductor layer and the high-resistance layer to the nitride semiconductor layer; an electron transport layer and an electron supply layer covering an upper portion of the p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the p-type nitride semiconductor layer; a potential fixing electrode in contact with the p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode.

Abstract: Disclosed is a high-resistance resistor based on silicon carbide. The resistor includes a semi-insulating 4H—SiC silicon carbide substrate, a silicon surface and a carbon surface of the silicon carbide substrate are provided with symmetrical atomic-thickness aluminum oxide insulating layers, thicknesses of the aluminum oxide insulating layers are 0.2 nm-2 nm, conductive metal electrodes are formed at two sides of the aluminum oxide insulating layers through evaporation, and thicknesses of the metal electrodes are 100 nm-500 nm. The present disclosure uses a high-resistance resistor based on silicon carbide that has the above structure, makes an ohmic contact electrode on a semi-insulating silicon carbide substrate, thus obtaining a resistor with a resistance of 100 T? or more, and satisfying requirements of the precision measurement industry.

Abstract: Methods of forming an oxide layer over a semiconductor substrate are provided. The method includes forming a first oxide containing portion of the oxide layer over a semiconductor substrate at a first growth rate by exposing the substrate to a first gas mixture having a first oxygen percentage at a first temperature. A second oxide containing portion is formed over the substrate at a second growth rate by exposing the substrate to a second gas mixture having a second oxygen percentage at a second temperature. A third oxide containing portion is formed over the substrate at a third growth rate by exposing the substrate to a third gas mixture having a third oxygen percentage at a third temperature. The first growth rate is slower than each subsequent growth rate and each growth rate subsequent to the second growth rate is within 50% of each other.

Abstract: A source-body self-aligned method of a VDMOSFET is provided. A pad layer and an unoxidized material layer are sequentially formed on an epitaxial layer on a semiconductor substrate. A lithography process is then carried out for patterning. Later, a thermal oxidation process is employed such that the unoxidized material layer is oxidized to form oxidation layers. Then, a source ion implantation process is performed, and a wet etching is used to remove the oxidation layers before successively employing a body ion implantation process. By using the process method disclosed in the present invention, it achieves to form the source region and the body region which are self-aligned. Meanwhile, since process complexity of the invention is relatively low, process uniformity and process cost can be optimally controlled. In addition, the invention achieves to reduce channel length and on-resistance, thereby enhancing the reliability effectively.

Abstract: A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.

Abstract: A phase change memory (PCM) device is provided. The PCM device includes a bottom electrode formed on a substrate, a heater electrode formed on the bottom electrode, the heater electrode having a tapered portion that becomes narrower in a direction away from the substrate. The PCM device also includes an interlayer dielectric (ILD) layer formed on the tapered portion of the heater electrode, the interlayer layer dielectric including an airgap that at least partially surrounds the tapered portion of the heater electrode. The PCM device also includes a phase change layer formed on the heater electrode, and a top electrode formed on the phase change layer.

Abstract: There is provided a technique that includes: forming a first film to have a first predetermined film thickness over a substrate by performing a first cycle a first predetermined number of times, the first cycle including non-simultaneously performing: (a1) forming an oxynitride film by supplying a first film-forming gas to the substrate; and (a2) changing the oxynitride film into a first oxide film by supplying a first oxidizing gas to the substrate to oxidize the oxynitride film.

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Abstract: A Junction Barrier Schottky device includes a semiconductor body of SiC having a first conductivity. An implanted region having a second conductivity, extends into the semiconductor body from a top surface of the semiconductor body to form a junction barrier diode with the semiconductor body. An electrical terminal is in ohmic contact with the implanted region and in direct electrical contact with the top surface, laterally to the implanted region, to form a Schottky diode with the semiconductor body. The implanted region is formed by a first and a second portion electrically connected directly to each other and aligned along an alignment axis transverse to the top surface. Orthogonally to the alignment axis, the first portion has a first maximum width and the second portion has a second maximum width greater than the first maximum width.

Abstract: A manufacturing method of a silicon nitride thin film, a thin film transistor, and a display panel are disclosed, the method including: providing a silane precursor into an atomic layer deposition apparatus for a preset time period, and remaining the silane precursor for a preset time period; providing an inert gas thereinto for a preset time period for the first time, and purging the silane precursor; providing a nitrogen supplying precursor for a preset time period, and remaining the nitrogen supplying precursor for a preset time period; providing the inert gas for a preset time period for the second time, and purging the nitrogen supplying precursor; repeating for a preset number of times the steps of providing the silane precursor, providing the inert gas for the first time, providing the nitrogen supplying precursor and providing the inert gas for the second time to form the silicon nitride thin film.

Abstract: Exemplary deposition methods may include introducing a vapor of a metal alkoxide into a processing volume of a semiconductor processing chamber. A substrate defining a trench may be housed in the processing volume. The methods may include condensing the vapor into a liquid metal alkoxide within the trench on the substrate. The methods may include forming a plasma external to the processing volume of the semiconductor processing chamber. The methods may include introducing plasma-generated species into the processing volume. The methods may include exposing the liquid metal alkoxide in the trench to the plasma-generated species. The methods may also include forming a metal oxide film in the trench through a reaction between the liquid metal alkoxide and the plasma-generated species.

Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency above 15 MHz. The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.0.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer over the metallization layer; forming a first sacrificial layer and a second sacrificial layer, each of which penetrates the upper dielectric layer and the metallization layer; removing the upper dielectric layer; forming a width controlling structure between the first sacrificial layer and the second sacrificial layer, wherein the width controlling structure defines a recess exposing the metallization layer; forming a protective layer within the recess of the width controlling structure; removing the width controlling structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first sacrificial layer and the second sacrificial layer.

Abstract: A method of gap filling a feature on a substrate decreases the feature-to-feature gap fill height variation by using a tungsten halide soak treatment. In some embodiments, the method may include heating a substrate to a temperature of approximately 350 degrees Celsius to approximately 450 degrees Celsius, exposing the substrate to a tungsten halide gas at a process pressure of approximately 5 Torr to approximately 25 Torr, soaking the substrate for a soak time of approximately 5 seconds to approximately 60 seconds with the tungsten halide gas, and performing a metal preclean process and a gap fill deposition on a plurality of features on the substrate after soaking of the substrate has completed.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC). The IC includes a pair of source/drain regions in a substrate. A gate dielectric layer is on the substrate and laterally between the source/drain regions. A gate electrode overlies the gate dielectric layer. A sidewall liner is disposed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer overlies the substrate and is on sidewalls and an upper surface of the sidewall liner. The sidewall spacer has a pair of segments respectively on opposite sides of the gate electrode. The sidewall spacer consists essentially of silicon oxycarbonitride. A dielectric constant of the sidewall spacer is greater than that of the sidewall liner.