Patents Examined by Asok K. Sarkar
  • Patent number: 11871567
    Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, and a top selective gate cut structure having a laminated structure embedded in an upper portion of the alternating layer stack and extending along a lateral direction. The laminated structure of the top selective gate cut structure comprises a dielectric filling wall and a dummy channel and a dummy functional layer on both sides of the dielectric filling wall.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: January 9, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kun Zhang
  • Patent number: 11862510
    Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; for a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventor: Mie Matsuo
  • Patent number: 11855189
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Patent number: 11855095
    Abstract: A semiconductor device includes a semiconductor substrate and a first dielectric layer. The semiconductor substrate includes at least one fin. The first dielectric layer is disposed on the at least one fin. A thickness of the first dielectric layer located on a top surface of the at least one fin is greater than a thickness of the first dielectric layer located on a sidewall of the at least one fin.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-I Lin, Chun-Heng Chen, Ming-Ho Lin, Chi-On Chui
  • Patent number: 11837466
    Abstract: There is provided a technique that includes: (a) supplying a silicon- and ligand-containing gas to a substrate having a surface on a first base and second base are exposed to adsorb silicon contained in the silicon- and ligand-containing gas on a surface of one of the first and second base; (b) supplying a fluorine-containing gas to the substrate after the silicon is absorbed, to cause the silicon to react with the fluorine-containing gas to modify the surface to be F-terminated; and (c) supplying a film-forming gas to the substrate after the surface is modified, to thereby form a film on a surface of the other of the first base and the second base, which is different from the one of the first base and the second base.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 5, 2023
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Kimihiko Nakatani
  • Patent number: 11837497
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, including a plurality of protrusions; a plurality of fins formed over the substrate and aligned with the plurality of protrusions; and an isolation structure formed on the substrate and between the protrusions and the fins. An orthographic projection of each of the plurality of fins and an orthographic projection of a corresponding protrusion of the plurality of protrusions on the substrate coincide with each other.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: December 5, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11830741
    Abstract: A method of selectively forming a film on a substrate includes: a preparation process of preparing a substrate having a surface to which a metal film and an insulating film are exposed; a first removal process of removing a natural oxide film on the metal film; a first film forming process of forming a self-assembled monolayer, which suppresses formation of a titanium nitride film, on the insulating film by providing the substrate with a compound for forming the self-assembled monolayer, the compound having a functional group containing fluorine and carbon; a second film forming process of forming a titanium nitride film on the metal film; an oxidation process of oxidizing the surface of the substrate; and a second removal process of removing a titanium oxide film, which is formed on the metal film and the self-assembled monolayer, by providing the surface of the substrate with the compound.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 28, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Shinichi Ike, Shuji Azumo, Yumiko Kawano, Hiroki Murakami
  • Patent number: 11824096
    Abstract: Field-effect transistors, and methods of forming such field-effect transistors, including a gate dielectric overlying a semiconductor material, and a control gate overlying the gate dielectric, wherein the control gate includes an instance of a first polycrystalline silicon-containing material consisting essentially of polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material selected from a group consisting of polycrystalline silicon-germanium and polycrystalline silicon-germanium-carbon.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Chandra Mouli
  • Patent number: 11823900
    Abstract: A method for printing a semiconductor material includes depositing a molten metal onto a substrate in an enclosed chamber to form a trace having a maximum height of 15 micrometers and/or a maximum width of 25 micrometers to 10 millimeters and/or a thin film having a maximum height of 15 micrometers. The method further includes reacting the molten metal with a gas phase species in the enclosed chamber to form the semiconductor material. The depositing the molten metal includes depositing a metal composition including the molten metal and an etchant or depositing the etchant separate from the molten metal in the enclosed chamber.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 21, 2023
    Assignee: The Johns Hopkins University
    Inventors: Jarod C. Gagnon, Michael J. Presley, Steven M. Storck, Jeffrey P. Maranchi, Korine A. Ohiri, Scott A. Shuler
  • Patent number: 11823913
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide methods of making an electronic device, and electronic devices made thereby, that comprise forming first and second encapsulating materials, followed by further processing and the removal of the entire second encapsulating material.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: November 21, 2023
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Bora Baloglu, Curtis Zwenger, Ronald Huemoeller
  • Patent number: 11823866
    Abstract: A substrate processing method for filling a gap without seams or voids comprising: providing a substrate with a gap in a reaction chamber, pumping down the reaction chamber to a pressure at or below 5 Torr and filling the gap with a film by alternately and sequentially supplying a precursor, a reactant and a radio frequency electromagnetic radiation comprising a relatively high radio frequency component and a relatively low radio frequency component.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 21, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: SungKyu Kang, JongWan Choi, YoungHoon Kim, HieChul Kim, KyungEun Lee, TaeHee Yoo
  • Patent number: 11810781
    Abstract: There is provided a technique that includes: forming a first film to have a first predetermined film thickness over a substrate by performing a first cycle a first predetermined number of times, the first cycle including non-simultaneously performing: (a1) forming an oxynitride film by supplying a first film-forming gas to the substrate; and (a2) changing the oxynitride film into a first oxide film by supplying a first oxidizing gas to the substrate to oxidize the oxynitride film.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: November 7, 2023
    Assignee: Kokusai Electric Corporation
    Inventors: Kiyohisa Ishibashi, Tsukasa Kamakura
  • Patent number: 11784042
    Abstract: Embodiments herein provide methods of depositing an amorphous carbon layer using a plasma enhanced chemical vapor deposition (PECVD) process and hard masks formed therefrom. In one embodiment, a method of processing a substrate includes positioning a substrate on a substrate support, the substrate support disposed in a processing volume of a processing chamber, flowing a processing gas comprising a hydrocarbon gas and a diluent gas into the processing volume, maintaining the processing volume at a processing pressure less than about 100 mTorr, igniting and maintaining a deposition plasma of the processing gas by applying a first power to one of one or more power electrodes of the processing chamber, maintaining the substrate support at a processing temperature less than about 350° C., exposing a surface of the substrate to the deposition plasma, and depositing an amorphous carbon layer on the surface of the substrate.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: October 10, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eswaranand Venkatasubramanian, Yang Yang, Pramit Manna, Kartik Ramaswamy, Takehito Koshizawa, Abhijit Basu Mallick
  • Patent number: 11784044
    Abstract: There is provided a technique that includes: forming a film on a substrate including a recess formed on a surface of the substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a precursor gas to the substrate; and (b) supplying a reaction gas to the substrate, wherein in (a), the precursor gas is supplied to the substrate separately a plurality of times, and a processing condition under which the precursor gas is supplied for a first time is set to a processing condition under which self-decomposition of the precursor gas is capable of being more suppressed than a processing condition under which the precursor gas is supplied for at least one subsequent time after the first time.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: October 10, 2023
    Assignee: Kokusai Electric Corporation
    Inventors: Takeo Hanashima, Kiyohisa Ishibashi
  • Patent number: 11776846
    Abstract: Methods and systems for manufacturing a structure comprising a substrate. The substrate comprises plurality of recesses and a plurality of lateral spaces. The recesses and lateral spaces are at least partially filled with a gap filling fluid.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: October 3, 2023
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Blanquart
  • Patent number: 11764056
    Abstract: There is provided a technique that includes: forming a first film to have a first predetermined film thickness over a substrate by performing a first cycle a first predetermined number of times, the first cycle including non-simultaneously performing: (a1) forming an oxynitride film by supplying a first film-forming gas to the substrate; and (a2) changing the oxynitride film into a first oxide film by supplying a first oxidizing gas to the substrate to oxidize the oxynitride film.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: September 19, 2023
    Assignee: Kokusai Electric Corporation
    Inventors: Kiyohisa Ishibashi, Tsukasa Kamakura
  • Patent number: 11764119
    Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: September 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungheon Lee, Jaekang Koh, Hyukwoo Kwon, Munjun Kim, Taejong Han
  • Patent number: 11749748
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: September 5, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: 11749693
    Abstract: Disclosed are a manufacturing method of an array substrate, an array substrate and a display device. The manufacturing method of the array substrate includes: providing a substrate; depositing and patterning a gate layer on the substrate; depositing a protective layer on the substrate covered with the gate layer by atomic layer deposition; and depositing and patterning an amorphous silicon layer and an ohmic contact layer on the protective layer. The uniform protective layer of the present disclosure reduces the influence on the field effect mobility of the thin film transistor, makes the display of the product more stable, and improves the display effect.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: September 5, 2023
    Assignees: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: Yuming Xia, En-tsung Cho, Lidan Ye
  • Patent number: 11749527
    Abstract: Methods and systems for forming complex oxide films are provided. Also provided are complex oxide films and heterostructures made using the methods and electronic devices incorporating the complex oxide films and heterostructures. In the methods pulsed laser deposition is conducted in an atmosphere containing a metal-organic precursor to form highly stoichiometric complex oxides.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 5, 2023
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Chang-Beom Eom, Jungwoo Lee