Patents Examined by Asok K. Sarkar
  • Patent number: 12040177
    Abstract: Methods for forming a laminate film on substrate by a plasma-enhanced cyclical deposition process are provided. The methods may include: providing a substrate into a reaction chamber, and depositing on substrate a metal oxide laminate film by alternatingly depositing a first metal oxide film and a second metal oxide film different from the first metal oxide film, wherein depositing the first metal oxide film and the second metal oxide film comprises, contacting the substrate with sequential and alternating pulses of a metal precursor and an oxygen reactive species generated by applying RF power to a reactant gas comprising at least nitrous oxide (N2O).
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: July 16, 2024
    Assignee: ASM IP Holding B.V.
    Inventor: Yoshio Susa
  • Patent number: 12033857
    Abstract: The present disclosure provides a processing method for semiconductor surface defects and a preparation method for semiconductor devices. The processing method for semiconductor surface defects includes: placing a semiconductor device in a plasma processing device, the semiconductor device comprising a semiconductor substrate and deposition layers formed on the surface of the semiconductor substrate, bubbles being formed in the deposition layers; and plasma bombarding the surface of the deposition layer to break the bubbles, so that the surface of the deposition layer is flat.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: July 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xianghong Jiang
  • Patent number: 12027365
    Abstract: Methods and related systems for filling a gap feature comprised in a substrate are disclosed. The methods comprise a step of providing a substrate comprising one or more gap features into a reaction chamber. The one or more gap features comprise an upper part comprising an upper surface and a lower part comprising a lower surface. The methods further comprise a step of subjecting the substrate to a plasma treatment. Thus, the upper surface is inhibited while leaving the lower surface substantially unaffected. Then, the methods comprise a step of selectively depositing a silicon-containing material on the lower surface.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: July 2, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Zecheng Liu, Sunja Kim, Viljami Pore, Jia Li Yao, Ranjit Borude, Bablu Mukherjee, René Henricus Jozef Vervuurt, Takayoshi Tsutsumi, Nobuyoshi Kobayashi, Masaru Hori
  • Patent number: 12027190
    Abstract: A first layer that includes a metal seed layer, a refractive seed or a refractive dopant is formed on a dielectric substrate. A peg of a near-field transducer is formed on the first layer such that a first surface of the peg is formed on and is in contact with the metal seed. An adhesive layer is formed over the peg using atomic layer deposition. The adhesive layer includes alumina and is 4 nm or less in thickness. A silicon dioxide overcoat is deposited over the adhesive layer. The alumina bonds the silicon dioxide to the peg.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: July 2, 2024
    Assignee: Seagate Technology LLC
    Inventor: Xiaoyue Huang
  • Patent number: 12020989
    Abstract: The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 25, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keng-Yao Chen, Chang-Yun Chang, Ming-Chang Wen
  • Patent number: 12014927
    Abstract: Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: June 18, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Rajesh Prasad, Sarah Bobek, Prashant Kumar Kulshreshtha, Kwangduk Douglas Lee, Harry Whitesell, Hidetaka Oshio, Dong Hyung Lee, Deven Matthew Raj Mittal, Scott Falk, Venkataramana R. Chavva
  • Patent number: 12014950
    Abstract: A method for forming a semiconductor structure includes the following steps: providing a substrate having a trench in a surface; forming an isolation layer on the surface of the substrate, the isolation layer covering a side wall and a bottom wall of the trench; pretreating the isolation layer such that an initial oxide layer is formed on a surface of the isolation layer; forming an advanced oxide layer on a surface of the initial oxide layer with an atomic layer deposition process; and forming a dielectric layer on a surface of the advanced oxide layer with a spin-on dielectrics (SOD) process such that the dielectric layer fills the trench.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 18, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shang Gao
  • Patent number: 12014928
    Abstract: Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 18, 2024
    Assignee: Lam Research Corporation
    Inventors: Xiaolan Ba, Ruopeng Deng, Juwen Gao, Sanjay Gopinath, Lawrence Schloss
  • Patent number: 12009265
    Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12009266
    Abstract: The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keng-Yao Chen, Chang-Yun Chang, Ming-Chang Wen
  • Patent number: 12009217
    Abstract: Provided are a substrate processing method and a substrate processing apparatus for forming a low-resistance metal-containing nitride film. The substrate processing method includes: a step of providing a substrate in a processing container; a step of forming a metal-containing nitride film on the substrate by repeating supplying an organic metal-containing gas and a nitrogen-containing gas alternately for a first predetermined number of cycles; a step of modifying the metal-containing nitride film by generating plasma in the processing container; and a step of repeating the step of forming the metal-containing nitride film and the step of modifying the metal-containing nitride film for a second predetermined number of cycles.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 11, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Tsuyoshi Takahashi, Yu Nunoshige
  • Patent number: 12009204
    Abstract: A method for improving a bias temperature instability of a SiO2 layer comprises exposing the SiO2 layer to atomic hydrogen.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: June 11, 2024
    Assignee: IMEC VZW
    Inventors: Jacopo Franco, Jean-Francois de Marneffe, Tibor Grasser
  • Patent number: 12002831
    Abstract: Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 4, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hajime Yamagishi, Eiji Sato, Akira Yamazaki, Takayuki Sekihara, Makoto Hayafuchi, Syunsuke Ishizaki
  • Patent number: 12004375
    Abstract: Provided is a pixel defining layer of an organic light-emitting diode display panel. The pixel defining layer includes: an insulating transparent cladding layer; and a reflecting layer in the transparent cladding layer, wherein the reflecting layer is configured to reflect light emitted from a light-emitting layer of the organic light-emitting diode display panel. Organic light-emitting diode display panels and methods for manufacturing an organic light-emitting diode display panel are also provided.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: June 4, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Biao Xu, Hungchieh Hu, Heng Yang
  • Patent number: 11987492
    Abstract: This disclosure describes a micromechanical device comprising a first device part and a second device part. One of the first and second device parts is a mobile rotor and the other of the first and second device parts is a fixed stator. The micromechanical device further comprises a motion limiter which extends from the first device part to the second device part. The motion limiter comprises an elongated lever, and the motion limiter is configured to bring a stopper into contact with a counter-structure by rotating the elongated lever.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 21, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Mikko Partanen
  • Patent number: 11984050
    Abstract: The present invention provides a product with incorporated operation display panel that further improves visibility at the time of light emission. The product with incorporated operation display panel includes a transparent conductive sheet, a display panel with a touch sensor furnished at least with light emitting elements consisting of light emitting elements arranged in two dimensions and being the product with incorporated operation display panel furnished with a thin layer that covers the total or a part of the front surface of a display panel, and a transparent substrate that forms a light guiding path is disposed at an opening between a transparent conductive sheet and a thin layer, or at an opening between a transparent conductive sheet and a light emitting device array substrate. The transparent base has micropores provided in a resin base material made of a transparent resin, and the micropores are formed by a lattice-like louver.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: May 14, 2024
    Assignee: Mui Lab, Inc.
    Inventor: Munehiko Sato
  • Patent number: 11978623
    Abstract: There is provided a technique that includes: forming an oxide film containing an atom X of a precursor on a substrate by performing a cycle a predetermined number of times. The cycle including non-simultaneously performing: (a) forming a first layer containing a component in which a first group is bonded to the atom X on the substrate by supplying the precursor having a molecular structure in which the first and second groups are bonded to the atom X, to the substrate, the first group containing an alkoxy group, and the second group containing at least one of an amino group, an alkyl group, a halogeno group, a hydroxy group, a hydro group, an aryl group, a vinyl group, and a nitro group; and (b) forming a second layer containing the atom X by supplying an oxidizing agent to the substrate to oxidize the first layer.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: May 7, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Katsuyoshi Harada, Kimihiko Nakatani, Yoshiro Hirose, Masaya Nagato, Takashi Ozaki, Tomiyuki Shimizu
  • Patent number: 11972944
    Abstract: A film having filling capability of a patterned recess on a surface of a substrate is deposited by forming a viscous material in a gas phase by striking a plasma in a chamber filled with a volatile precursor that can be polymerized within certain parameter ranges which include a partial pressure of the precursor during a plasma strike and substrate temperature.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: April 30, 2024
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart
  • Patent number: 11967499
    Abstract: There is provided a technique that includes (a) forming a first film having a first thickness on an underlayer by supplying a first process gas not including oxidizing gas to a substrate, wherein the first film contains silicon, carbon, and nitrogen and does not contain oxygen, and the underlayer is exposed on a surface of the substrate and is at least one selected from the group of a conductive metal-element-containing film and a nitride film; and (b) forming a second film having a second thickness larger than the first thickness on the first film by supplying a second process gas including oxidizing gas to the substrate, wherein the second film contains silicon, oxygen, and nitrogen, and wherein in (b), oxygen atoms derived from the oxidizing gas and diffuse from a surface of the first film toward the underlayer are absorbed by the first film and the first film is modified.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: April 23, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Tatsuru Matsuoka
  • Patent number: 11967502
    Abstract: Methods of forming a material layer according to some embodiments of the inventive concept may include a deposition cycle including providing an adsorption inhibitor on a substrate, purging an excess amount of the adsorption inhibitor, providing a metal precursor on the substrate, purging an excess amount of the metal precursor, and supplying a reactant to form a material layer on the substrate. The adsorption inhibitor may include a group 15 element or a group 16 element.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 23, 2024
    Assignees: Samsung Electronics Co., Ltd., ADEKA CORPORATION
    Inventors: Younsoo Kim, Jaewoon Kim, Haeryong Kim, Jinho Lee, Tsubasa Shiratori