Patents Examined by Asok Sarkar
  • Patent number: 8390122
    Abstract: Methods are generally provided for forming a conductive oxide layer on a substrate. In one particular embodiment, the method can include sputtering a transparent conductive oxide layer (e.g., including cadmium stannate) on a substrate from a target in a sputtering atmosphere comprising cadmium. The transparent conductive oxide layer can be sputtered at a sputtering temperature greater of about 100° C. to about 600° C. Methods are also generally provided for manufacturing a cadmium telluride based thin film photovoltaic device.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: March 5, 2013
    Assignee: Primestar Solar, Inc.
    Inventor: Scott Daniel Feldman-Peabody
  • Patent number: 8361872
    Abstract: A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Toshiharu Furukawa, Robert R. Robison
  • Patent number: 8357548
    Abstract: A semiconductor wafer metrology technique comprising performing atmospheric buoyancy compensated weighing of a wafer, in which the wafer is weighed in a substantially upright condition. A vertical or near vertical wafer orientation causes the surface area in the direction of a force (weight) sensor to be reduced compared with a horizontal wafer orientation. Hence, the electrostatic force components acting in the same direction as the wafer weight force component is reduced.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: January 22, 2013
    Assignee: Metryx Limited
    Inventor: Robert John Wilby
  • Patent number: 8354738
    Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: January 15, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 8351624
    Abstract: An audio output apparatus which outputs an audio signal to an audio control apparatus controlling processing of the audio signal, and to which an external device having an external terminal is connectable includes an output terminal, a detecting section, a generating section, and a transmitting section. The output terminal is connected with the external terminal and outputs the audio signal to the external device via the external terminal. The detecting section detects whether or not the external terminal is connected to the output terminal. The generating section generates a control signal based on a result of the detection by the detecting means. The transmitting section transmits the generated control signal to the audio control apparatus in order that the audio control apparatus controls the processing of the audio signal based on the control signal.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: January 8, 2013
    Assignee: Sony Corporation
    Inventor: Kensuke Motomura
  • Patent number: 8338268
    Abstract: A transfer process for silicon nanomembranes (SiNM) may involve treating a recipient substrate with a polymer structural support. After treating the recipient substrate, a substrate containing the intended transferable devices may be brought in direct contact with the aforementioned polymer layer. The two substrates may then go through a Deep Reactive Ion Etch (DRIE) to remove at least a portion of the substrate containing the devices. Oxide may be selectively removed with a buffered oxide wet etch, leaving the transferred SiNM on the recipient substrate with the Underlying polymer layer.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 25, 2012
    Assignee: Lumilant, Inc.
    Inventors: Mathew Joseph Zablocki, Ahmed Sharkawy, Dennis W. Prather
  • Patent number: 8338291
    Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: December 25, 2012
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Patent number: 8334593
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: December 18, 2012
    Assignee: General Electric Company
    Inventors: Paul Alan McConnelee, Arun Virupaksha Gowda
  • Patent number: 8329589
    Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio Luis Pacheco Rotondaro, Tracy Q. Hurd, Elizabeth Marley Koontz
  • Patent number: 8329494
    Abstract: A method for manufacturing a solar cell including a substrate, a first electrode layer, a semiconductor layer, and a second electrode layer, includes forming a first sacrificial layer on a portion of a surface of the substrate; forming the first electrode layer on the substrate and on the first sacrificial layer; and dividing the first electrode layer by removing the first sacrificial layer and a portion of the first electrode layer formed on the first sacrificial layer.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: December 11, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Atsushi Denda, Hiromi Saito
  • Patent number: 8324522
    Abstract: Provided is an apparatus for performing a reflow process of a solder ball provided to a semiconductor chip. The reflow apparatus may include a coil, a support member and a moving member. The coil may receive a current from a power supply to heat the solder ball using an induced heating method. The support member may be disposed on the front or the rear of the coil and may support a printed circuit board on which a semiconductor chip is mounted. The moving member may move the printed circuit board so that the printed circuit object passes through an internal space surrounded by the coil.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minill Kim, Kwang Yong Lee, Jonggi Lee, Ji-Seok Hong
  • Patent number: 8319280
    Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: November 27, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
  • Patent number: 8319264
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: November 27, 2012
    Assignee: SK Hynix Inc.
    Inventor: Seung Bum Kim
  • Patent number: 8309460
    Abstract: Provided are methods of manufacturing semiconductor devices by which two different kinds of contact holes with different sizes are formed using one photolithography process. The methods include preparing a semiconductor substrate in which an active region is titled in a diagonal direction. A hard mask is formed on the entire surface of the semiconductor substrate. A mask hole is patterned not to overlap a word line. A first oxide layer is deposited on the hard mask, and the hard mask is removed to form a piston-shaped sacrificial pattern. A first polysilicon (poly-Si) layer is deposited on the sacrificial pattern and patterned to form a cylindrical first sacrificial mask surrounding the piston-shaped sacrificial pattern. A second oxide layer is coated on the first sacrificial mask to such an extent as to form voids. A second poly-Si layer is deposited in the voids and patterned to form a pillar-shaped second sacrificial mask. The second oxide layer is removed to expose the active region.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Ik Kim, Ho-Jun Yi
  • Patent number: 8309433
    Abstract: A method of manufacturing an optical sensor includes the steps of providing a semiconductor wafer having a plurality of pixel areas; forming a grid-like rib enclosing each pixel area on the semiconductor wafer, the grid-like rib having a predetermined width and being formed from a fixing member; providing a light-transmissive substrate having a gap portion on a main surface thereof, the gap portion having at least one of a groove having a width smaller than the grid-like rib and a plurality of through-holes; fixing the semiconductor wafer and the light-transmissive substrate such that the grid-like rib and the gap portion face each other; and cutting the fixed semiconductor wafer and light-transmissive substrate into pieces such that each piece includes one pixel area.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: November 13, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Matsuki, Takanori Suzuki, Koji Tsuduki, Shin Hasegawa, Tadashi Kosaka, Akiya Nakayama
  • Patent number: 8309378
    Abstract: A method of fabricating light emitting diode chips having a phosphor coating layer comprises providing a substrate having a plurality of light emitting diodes formed thereon; forming a conductive bump on at least one of the plurality of light emitting diodes; forming a phosphor coating layer over the substrate and the light emitting diodes; cutting the phosphor coating layer by a point cutter to remove an upper portion of the phosphor coating layer, so as to reduce a thickness of the phosphor coating layer and expose the conductive bump; and forming a plurality of individual light emitting diode chips having the phosphor coating layer by separating the plurality of light emitting diodes.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: November 13, 2012
    Assignee: Everlight Electronics Co., Ltd.
    Inventor: Chung-Chuan Hsieh
  • Patent number: 8304352
    Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Kazuhiro Matsuo, Yoshio Ozawa
  • Patent number: 8304780
    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: November 6, 2012
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
  • Patent number: 8298849
    Abstract: Methods for forming Cu—In—Ga—N (CIGN) layers for use in TFPV solar panels are described using reactive PVD deposition in a nitrogen containing atmosphere. In some embodiments, the CIGN layers can be used as an absorber layer and eliminate the need of a selenization step. In some embodiments, the CIGN layers can be used as a protective layer to decrease the sensitivity of the CIG layer to oxygen or moisture before the selenization step. In some embodiments, the CIGN layers can be used as an adhesion layer to improve the adhesion between the back contact layer and the absorber layer.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: October 30, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Guowen Ding, Hien Minh Huu Le, Guizhen Zhang
  • Patent number: 8293565
    Abstract: A manufacturing method for a solid-state imaging device according to an embodiment of the present invention includes a step of forming a transparent resin layer above a principal surface of a semiconductor substrate, a step of exposing the transparent resin layer to light by using a grating mask having a first transmission region and a second transmission region having a higher transmittance of the light than the first transmission region in mutually separate positions, a step of forming first resin patterns and second resin patterns lower than the first resin patterns in mutually separate positions, and a step of forming first microlenses and second microlenses lower than the first microlenses.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hajime Ootake