Abstract: A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric layer over a substrate; forming a dual storage node contact plug to be buried in the interlayer dielectric layer, forming a first damascene pattern to isolate the dual storage node contact plug, forming a protective layer pattern inside the first damascene pattern, etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern, and forming bit lines inside the first and second damascene patterns.

Abstract: A rotor blade suitable for use in a gas turbine engine includes an attachment section which defines at least one internal cooling passage along a passage axis through the attachment section.

Abstract: A method of fabricating a semiconductor device package is provided. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having a dielectric film outer surface and a first metal layer outer surface; forming a plurality of vias extending through the laminate according to a predetermined pattern; attaching one or more semiconductor device to the dielectric film outer surface such that the semiconductor device contacts one or more vias after attachment; disposing an electrically conductive layer on the first metal layer outer surface and on an inner surface of the plurality of vias to form an interconnect layer comprising the first metal layer and the electrically conductive layer; and patterning the interconnect according to a predetermined circuit configuration to form a patterned interconnect layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device.

Abstract: A method for semiconductor fabrication using a trench first metal hard mask (TFMHM) process for damascene structures includes forming a secondary metal hard mask layer above a first metal hard mask layer after trench opening for the via (and trench) etching. The secondary metal hard mask layer is formed of metal material substantially resistant to the etching process which enables via etching to self-align (using an edge of the secondary metal mask layer). In one embodiment, the secondary metal mask layer is formed using an electroless deposition process, and may include nickel (Ni), cobalt (Co), gold, (Au), palladium (Pd), cadmium (Cd) silver (Ag), ruthenium (Ru), and alloys and/or combinations thereof. Because the first metal hard mask is usually formed of TiN, the trench and via etching process removes a significant amount of the TiN layer. Utilization of the secondary metal hard mask to protect the first metal hard mask layer further enables a reduction in the thickness of the first metal hard mask layer.

Abstract: In one embodiment a method for fabricating a compound nitride semiconductor device comprising positioning one or more substrates on a susceptor in a processing region of a metal organic chemical vapor deposition (MOCVD) chamber comprising a showerhead, depositing a gallium nitride layer over the substrate with a thermal chemical-vapor-deposition process within the MOCVD chamber by flowing a first gallium containing precursor and a first nitrogen containing precursor through the showerhead into the MOCVD chamber, removing the one or more substrates from the MOCVD chamber without exposing the one or more substrates to atmosphere, flowing a chlorine gas into the processing chamber to remove contaminants from the showerhead, transferring the one or more substrates into the MOCVD chamber after removing contaminants from the showerhead, and depositing an InGaN layer over the GaN layer with a thermal chemical-vapor-deposition process within the MOCVD chamber is provided.

Abstract: A turbine for use with a turbine generator, the turbine including at least one turbine blade for positioning in a flowpath, a hub mounting the at least one turbine blade, and a rotatable shaft in operational communication with the hub via a hinge assembly, an axis of the hub being independent of an axis of the shaft. The hinge assembly is disposed between the shaft and the hub and configured to adjust an angle therebetween. A controller assembly is configured to adjust at least one operational characteristic of the hinge assembly during turbine operation. In one embodiment the operational characteristic is a teeter angle of the hinge assembly. In one embodiment operational characteristic is a stiffness or damping force. Methods for using and controlling a fluid turbine are also disclosed.

Abstract: A buoyant hydro turbine(31) for capturing and utilizing energy in the currents of flowing water. A driven component(33) produces electricity or other energy is coupled to and supported by a buoyant rotor(64), increasing efficiency and eliminating the need for an independent supporting structure. Tethered in flowing water, the current(71) rotates the rotors(32) and transfers rotatable energy to the central driven component(33) where electricity or other mechanical work is produced. A number of embodiments are adapted for optimizing and maintaining positioning in a stream of moving water. Additional embodiments optimizing the efficiency and effectiveness of the turbine in capturing and utilizing the current's kinetic energy as well as hydrostatic pressure.

Abstract: An example turbine blade includes a blade having an airfoil profile extending radially toward a blade tip. A shelf is established in the blade tip. A sealing portion of the blade tip extends radially past a floor of the shelf. The sealing portion extends from a blade tip leading edge to a blade tip trailing edge. A groove is established in the blade tip. The groove extends from adjacent the shelf to adjacent the blade tip trailing edge. The groove is configured to communicate a fluid from a position adjacent the shelf to a position adjacent the blade tip trailing edge.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.

Abstract: Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer, depositing an insulating layer over the conductive barrier layer, creating an opening in the insulating layer to expose the conductive barrier layer, and forming a via contact in the opening. The conductive barrier layer protects the metal layer by preventing the formation of an oxide layer, which could reduce conductivity.

Abstract: A method of forming a well-anchored carbon nanotube (CNT) array, as well as thermal interfaces that make use of CNT arrays to provide very high thermal contact conductance. A thermal interface is formed between two bodies by depositing a continuous array of carbon nanotubes on a first of the bodies so that, on mating the bodies, the continuous array is between surface portions of the first and second bodies. The thermal interface preferably includes a multilayer anchoring structure that promotes anchoring of the continuous array of carbon nanotubes to the first body. The anchoring structure includes a titanium bond layer contacting the surface portion of the first body, and an outermost layer with nickel or iron catalytic particles from which the continuous array of carbon nanotubes are nucleated and grown. Additional thermal interface materials (TIM's) can be used in combination with the continuous array of carbon nanotubes.

Abstract: A method for manufacturing a substrate of a semiconductor device is provided, which comprises a step of forming a fragile layer in a semiconductor substrate by irradiating the semiconductor substrate with ion species, a step of forming a bonding layer over the semiconductor substrate, a step of bonding the semiconductor substrate and a substrate having an insulating surface with the bonding layer interposed therebetween, a step of separating the semiconductor substrate with a semiconductor layer left over the substrate having the insulating surface by heating at least the semiconductor substrate, and a step of reprocessing the semiconductor substrate from which the semiconductor layer is separated.

Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Abstract: A method for manufacturing a thin film transistor containing an channel layer 11 having indium oxide, including forming an indium oxide film as an channel layer and subjecting the formed indium oxide film to an annealing in an oxidizing atmosphere.

Abstract: One aspect of the invention includes a copper substrate; a catalyst on top of the copper substrate surface; and a thermal interface material that comprises a layer containing carbon nanotubes that contacts the catalyst. The carbon nanotubes are oriented substantially perpendicular to the surface of the copper substrate. A Raman spectrum of the layer containing carbon nanotubes has a D peak at ˜1350 cm?1 with an intensity ID, a G peak at ˜1585 cm?1 with an intensity IG, and an intensity ratio ID/IG of less than 0.7 at a laser excitation wavelength of 514 nm. The thermal interface material has: a bulk thermal resistance, a contact resistance at an interface between the thermal interface material and the copper substrate, and a contact resistance at an interface between the thermal interface material and a solid-state device. A summation of these resistances has a value of 0.06 cm2K/W or less.

Abstract: A turbine rotor blade with an airfoil cooling circuit and a platform cooling circuit formed integral with each other such that only one cooling flow is used. The airfoil cooling circuit includes a 5-pass aft flowing serpentine circuit with a first leg located adjacent to the leading edge region. The platform includes a mid section platform cooling circuit and an aft section platform cooling circuit. Cooling air from the second leg flows into the mid section platform cooling circuit and then into the third leg, turns at the blade tip and flows from the fourth leg into the aft section platform cooling circuit, and then into the fifth leg and up toward the blade tip. Cooling air from the fifth leg is bled off through rows of multiple impingement holes in the trailing edge and then discharged through exit holes or slots formed along the trailing edge.

Abstract: Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof. The temperature range described above may be between about 20° C.

Abstract: Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.