Patents Examined by Asok Sarkar
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Patent number: 8178425Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.Type: GrantFiled: January 21, 2011Date of Patent: May 15, 2012Assignee: Disco CorporationInventors: Tasuku Koyanagi, Hiroshi Morikazu
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Patent number: 8173469Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.Type: GrantFiled: March 17, 2011Date of Patent: May 8, 2012Assignee: LG Innotek Co., Ltd.Inventors: Kyung Wook Park, Myung Hoon Jung
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Patent number: 8173474Abstract: When a layered structure of a transparent electrode layer and a metal layer is formed as a back side electrode layer over a surface on a side opposite to a side of incidence of light of a thin film solar battery, a time when formation of the transparent electrode layer is completed and a time when formation of the metal layer is started are made to coincide for one substrate.Type: GrantFiled: March 30, 2010Date of Patent: May 8, 2012Assignee: Sanyo Electric Co., Ltd.Inventor: Kazushige Kaneko
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Patent number: 8172505Abstract: In this cooling structure, a cooling flow path, which is meandering around a flow direction of a high temperature combustion gas, is provided in a structural body. The cooling flow path has an inflow path for a cooling air formed inside of the structural body; at least one straight flow path provided with intervals with respect to an axial line; and a turning flow path for communicating the end portions of the inflow path with the straight flow path or communicating with the end portions of the straight flow paths one after another.Type: GrantFiled: February 7, 2007Date of Patent: May 8, 2012Assignees: IHI Corporation, Japan Aerospace Exploration AgencyInventors: Shu Fujimoto, Yoshitaka Fukuyama, Takashi Yamane, Masahiro Matsushita, Toyoaki Yoshida
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Patent number: 8173524Abstract: Methods form epitaxial materials by forming at least two gate stacks on a silicon substrate and forming sidewall spacers on sides of the gate stacks. Such methods pattern a recess in the silicon substrate between adjacent ones of the gate stacks. The methods also provide a liner in a bottom of the recess, and epitaxially grow epitaxial material from sidewalls of the recess to fill the recess with the epitaxial material.Type: GrantFiled: January 11, 2011Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Anthony I. Chou, Abhishek Dube, Dominic J. Schepis
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Patent number: 8174094Abstract: An electronic device comprises a substrate comprising a first surface and a second surface, a substrate carrier comprising a first surface and a second surface, and an inorganic material bonding the second surface of the substrate and the second surface of the substrate carrier.Type: GrantFiled: June 21, 2009Date of Patent: May 8, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chien-Hua Chen, Barry C. Snyder, Ronald A. Hellekson
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Patent number: 8164188Abstract: A method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.Type: GrantFiled: November 23, 2009Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
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Patent number: 8164132Abstract: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.Type: GrantFiled: March 28, 2011Date of Patent: April 24, 2012Assignee: Round Rock Research, LLCInventor: H. Montgomery Manning
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Patent number: 8163569Abstract: Provided are a magnetic memory device and a method of forming the same. The method may include forming a pinning pattern on a substrate; forming a first interlayer insulating layer that exposes the pinning pattern on the substrate; forming a pinned layer, a tunneling barrier layer and a second magnetic conductive layer on the pinning pattern; and forming a pinned pattern, a tunnel barrier pattern and a second magnetic conductive pattern by performing a patterning process on the pinned layer, the tunnel barrier layer and the second magnetic conductive layer.Type: GrantFiled: March 17, 2011Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: KyungTae Nam, Byeungchul Kim, Seung-Yeol Lee
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Patent number: 8163634Abstract: A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface.Type: GrantFiled: July 19, 2010Date of Patent: April 24, 2012Assignee: Alcatel LucentInventors: Jorge Manuel Garcia, Loren N. Pfeiffer
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Patent number: 8163626Abstract: Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.Type: GrantFiled: June 15, 2010Date of Patent: April 24, 2012Assignee: Applied Materials, Inc.Inventors: Johanes Swenburg, David Chu, Theresa Kramer Guarini, Yonah Cho, Udayan Ganguly, Lucien Date
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Patent number: 8163648Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.Type: GrantFiled: June 17, 2011Date of Patent: April 24, 2012Assignee: Micron Technology, Inc.Inventor: Guy T. Blalock
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Patent number: 8158490Abstract: A method for producing a Group III nitride-based compound semiconductor device includes, before bonding a support substrate to an epitaxial layer formed on an epitaxial growth substrate, forming trenches in such a manner as to extend from the top surface of a stacked structure including the epitaxial layer to at least the interface between the epitaxial growth substrate and the bottom surface of the epitaxial layer. The trenches divide the epitaxial layer into extended device areas which encompass respective product device structures, and stress relaxation areas. A plurality of laser irradiations are performed for laser lift-off such that, after each laser irradiation, the expanded device areas and the stress relaxation areas are formed by a laser-irradiated area and a laser-unirradiated area, and a strip-shaped laser-unirradiated stress relaxation area is formed at a boundary between the laser-irradiated area and the laser-unirradiated area.Type: GrantFiled: March 30, 2010Date of Patent: April 17, 2012Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Umemura, Masahiro Ohashi
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Patent number: 8147205Abstract: The turbomachine blade has ribs formed in the vicinity of the trailing edge. Over the major fraction of the trailing edge (42), in zones where the temperature in operation is particularly high, the ends (53) of the ribs are closer to the trailing edge and/or the sections of the ribs (F) are greater. Thereby, the design of the blade is optimized and the lifetime thereof is increased.Type: GrantFiled: November 26, 2008Date of Patent: April 3, 2012Assignee: SNECMAInventors: Sébastien Digard Brou De Cuissart, Matthieu Le Ray
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Patent number: 8143686Abstract: In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods.Type: GrantFiled: October 18, 2010Date of Patent: March 27, 2012Assignee: President and Fellows of Harvard CollegeInventors: Eric Mazur, Mengyan Shen
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Patent number: 8143150Abstract: A method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region. The semiconductor substrate is etched to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns. An isolation layer filling the first and second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively is formed.Type: GrantFiled: January 17, 2011Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Hoon Jeong
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Patent number: 8133023Abstract: An apparatus and method for reducing wind turbine damage includes a propeller having a plurality of blades projecting radially from a hub. The blades may be adjustably combined to form variable cross-sections that either increase or decrease propeller rotation speed dependent on wind speed and weather conditions.Type: GrantFiled: April 3, 2009Date of Patent: March 13, 2012Assignee: Lockheed Martin CorporationInventor: Elliott Reitz
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Patent number: 8133027Abstract: A propeller system includes a propeller hub which supports a multiple of propeller blades. A tailshaft extends from a propeller hub portion of the propeller hub along an axis of rotation with a propeller pitch change yoke mounted within the propeller hub for movement along an axis of rotation to change a pitch of the multiple of propeller blades, the propeller pitch change yoke in sliding engagement with the tailshaft.Type: GrantFiled: April 13, 2009Date of Patent: March 13, 2012Assignee: Hamilton Sundstrand CorporationInventors: Paul A. Carvalho, David V. Arel
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Patent number: 8133008Abstract: An axial flow fluid apparatus axially provided with a plurality of blade rows having a plurality of blades arranged around a shaft is provided. A fluid passage for jetting a fluid to a downstream velocity defect region resulting from a blade is formed in at least one of blades constituting a blade row installed on the upstream side of the plurality of blade rows so as to lead from a positive pressure surface to a negative pressure surface or a trailing edge.Type: GrantFiled: March 5, 2007Date of Patent: March 13, 2012Assignee: IHI CorporationInventor: Naoki Tsuchiya
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Patent number: 8129284Abstract: A semiconductor wafer in which a carbon thin film is formed on a surface of a silicon substrate implanted with impurities is irradiated with flash light emitted from flash lamps. Absorbing the flash light causes the temperature of the carbon thin film to increase. The surface temperature of the silicon substrate implanted with impurities is therefore increased to be higher than that in a case where no thin film is formed, and the sheet resistance value can be thereby decreased. When the semiconductor wafer with the carbon thin film formed thereon is irradiated with flash light in high concentration oxygen atmosphere, since the carbon of the thin film is oxidized to be vaporized, removal of the thin film is performed concurrently with flash heating.Type: GrantFiled: March 26, 2010Date of Patent: March 6, 2012Assignee: Dainippon Screen Mfg. Co., Ltd.Inventor: Shinichi Kato