Abstract: Methods are generally provided for forming a conductive oxide layer on a substrate. In one particular embodiment, the method can include sputtering a transparent conductive oxide layer (e.g., including cadmium stannate) on a substrate from a target in a sputtering atmosphere comprising cadmium. The transparent conductive oxide layer can be sputtered at a sputtering temperature greater of about 100° C. to about 600° C. Methods are also generally provided for manufacturing a cadmium telluride based thin film photovoltaic device.

Abstract: A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature.

Abstract: Heat sink structures employing carbon nanotube or nanowire arrays to reduce the thermal interface resistance between an integrated circuit chip and the heat sink are disclosed. Carbon nanotube arrays are combined with a thermally conductive metal filler disposed between the nanotubes. This structure produces a thermal interface with high axial and lateral thermal conductivities.

Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

Abstract: Wind turbine blade (11) with a flashing beacon on its tip which is connected to the wind turbine rotor hub (13) where this beacon includes a lighting module (21) in the tip area of the blade (11) which is supplied by a device that includes a light emitter (23) situated in the hub (13) or in the root area of the blade (11), a light to electrical energy converter (27) connected directly to this lighting module (21) and a conductor (25) of light but not electrical energy from this light emitter (23) to this converter (27).

Abstract: Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping (ART) and epitaxial layer overgrowth (ELO). In general, in a first aspect, embodiments of the invention may include a method of forming a structure. The method includes forming a first opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semi-conductor material lattice-mismatched to the first semiconductor material, is formed within the first opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer.

Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.

Abstract: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a plasma state including oxygen and silicon on an inner surface of the trench while applying no bias voltage (or a relatively low voltage), and a second step of filling the material in a plasma state including oxygen and silicon in the trench while applying a bias voltage (or a relatively high voltage).

Abstract: A method of fabricating light emitting diode chips having a phosphor coating layer comprises providing a substrate having a plurality of light emitting diodes formed thereon; forming a conductive bump on at least one of the plurality of light emitting diodes; forming a phosphor coating layer over the substrate and the light emitting diodes; cutting the phosphor coating layer by a point cutter to remove an upper portion of the phosphor coating layer, so as to reduce a thickness of the phosphor coating layer and expose the conductive bump; and forming a plurality of individual light emitting diode chips having the phosphor coating layer by separating the plurality of light emitting diodes.

Abstract: A turbine rotor blade with a low cooling flow serpentine circuit to provides cooling for the airfoil. The circuit includes a three pass aft flowing serpentine circuit that begins at the airfoil mid-chord region and connects to a series of multiple impingement cooling holes formed within the trailing edge region. A double pass forward flowing serpentine circuit then connects with the triple pass aft flowing serpentine circuit to provide cooling for the leading edge region and is connected to a showerhead arrangement for discharging film cooling air. A blade tip cooling channel connects with the last leg of the double pass forward flowing serpentine to form a 6-pass serpentine flow cooling circuit for the entire blade. Since only the leading edge serpentine channel discharges film cooling air, the serpentine circuit can make use of low cooling flow to provide cooling for the entire blade.

Abstract: Provided is a susceptor 13 for manufacturing an epitaxial wafer, comprising a mesh-like groove 13b on a mount face on which a silicon substrate W is to be mounted, wherein a coating H of silicon carbide is formed on the mount face, and the coating has a surface roughness of 1 ?m or more in centerline average roughness Ra and a maximum height of a protrusion 13p generated in forming the coating H of 5 ?m or less. Thus, defects such as warping and slip as well as adhesion of the silicon substrate to the susceptor are prevented.

Abstract: A turbine rotor blade with a low cooling flow serpentine circuit to provides cooling for the airfoil. The circuit includes a first 3-pass serpentine flow circuit with a first leg located adjacent to the leading edge to provide impingement cooling air into a leading edge impingement cavity. The remaining cooling air flows through the first serpentine circuit to provide cooling for the blade forward mid-chord region and is discharged through film cooling holes on the pressure and suction side walls. Some of the impingement cooling air for the leading edge is discharged as film cooling air for the leading edge surface while the remaining spent cooling air flows through a blade tip channel and then into the second aft flowing 3-pass serpentine circuit to provide impingement cooling for the trailing edge region before being discharged out through exit slots and blade tip corner discharge holes.

Abstract: The present invention advantageously provides for, in different embodiments, low-cost deposition techniques to form high-quality, dense, well-adhering Group IBIIIAVIA compound thin films with macro-scale as well as micro-scale compositional uniformities. It also provides methods to monolithically integrate solar cells made on such compound thin films to form modules. In one embodiment, there is provided a method of growing a Group IBIIIAVIA semiconductor layer on a base, and includes the steps of depositing on the base a nucleation and/or a seed layer and electroplating over the nucleation and/or the seed layer a precursor film comprising a Group IB material and at least one Group IIIA material, and reacting the electroplated precursor film with a Group VIA material. Other embodiments are also described.

Abstract: A method for manufacturing a semiconductor device, comprising: loading a wafer to be subjected to film formation to a chamber; supporting the wafer to be spaced from a film formation position of the wafer; preliminarily heating the wafer while rotating a rotating member for rotating the wafer through a supporting member during the film formation at a predetermined rotational speed under a state of the wafer to be spaced from the film formation position; placing the wafer on the supporting member in the film formation position; and heating the wafer at a predetermined temperature and supplying a process gas onto the wafer while rotating the wafer.

Abstract: The present invention provides a method for manufacturing a resistance change element that can reduce occurrence of corrosion without increasing a substrate temperature. A laminate film that includes a high melting-point metal film and a metal oxide film, is etched using a mask under a plasma atmosphere formed using any one of a mixture gas formed by adding at least one gas selected from the group consisting of Ar, He, Xe, Ne, Kr, O2, O3, N2, H2O, N2O, NO2, CO and CO2 to at least one kind of gasified compound selected from alcohol and hydrocarbon or the gas compound.