Abstract: A turbine rotor blade with a leading edge region cooled by a series of impingement cooling cavities that repeats from near the platform to the blade tip to provide impingement cooling for the leading edge without a loss of cooling air flow volume. A cooling supply cavity delivers cooling air to a series of impingement cavities located on the pressure side, the leading edge and the suction side of the airfoil in a series flow. The spent cooling air from the series then flows up into the next series of impingement cavities to provide impingement cooling to the next section of the leading edge. The cooling air flows through multiple series of impingement cooling cavities until the blade tip, which then discharges the spent impingement cooling air through tip cooling holes.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer deposition.

Abstract: A gas turbine engine component having shaped cooling holes that further enhances the cooling of a desired region while reducing stress levels in and around the cooling holes is disclosed. The cooling holes are generally elliptically-shaped and diffuse from a cooling fluid supply side to a discharge side and are oriented on the turbine component to reduce stress concentrations while directing the cooling fluid to a desired surface or location. The elliptical cooling holes have openings in the surface that have high points that are concentric and planar.

Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

Abstract: A metered cooling slot disposed in a wall comprising an outer surface that is exposed to a hot gas stream and an inner surface that defines an internal coolant chamber through which a coolant passes, the metered cooling slot comprising: a slot formed within the outer surface elongated in a first direction, the slot comprising a pair of spaced apart, opposing, slot surfaces and a base, the slot surfaces intersecting the outer surface to form a slot outlet opposite the base; and two or more metering apertures formed within the wall, each metering aperture intersecting the inner surface of the wall to form a metering aperture inlet and intersecting one of the pair of slot surfaces to form a metering aperture outlet; wherein: D represents the approximate diameter of at least two of the metering apertures; P represents the approximate distance between the center lines of at least two neighboring metering apertures; and P/D comprises a value within the range of about 4 to 6.

Abstract: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.

Abstract: A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Abstract: In a method of manufacturing a semiconductor device, a first groove and a second groove each having a width less than that of a scribe line are formed along the scribe line in a first protective film provided below a second protective film which protects element forming regions when a wafer is divided into parts by a laser dicing, and the first groove and the second groove are filled with the second protective film. Then, the laser dicing is performed on a region between the first groove and the second groove along the scribe line from the surface where the second protective film is formed to form a cutting groove that reaches at least a predetermined depth of the multi-layer interconnect.

Abstract: Methods are generally provided for forming a conductive oxide layer on a substrate. In one particular embodiment, the method can include sputtering a transparent conductive oxide layer on a substrate at a sputtering temperature from about 50° C. to about 250° C., and annealing the transparent conductive oxide layer at an anneal temperature of about 450° C. to about 650° C. Methods are also generally provided for manufacturing a cadmium telluride based thin film photovoltaic device.

Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Abstract: A method of fabricating a joined wafer has an exposure process which comprises a device formed-area exposure process of exposing by a stepper such that parts of the photosensitive adhesive layer formed over a surface of the transparent wafer or the device formed wafer are removed, the parts corresponding to the device formed areas when the transparent wafer and the device formed wafer are stuck together; and a wafer periphery exposure process of exposing such that a portion of the photosensitive adhesive layer over the periphery of the transparent wafer is left.

Abstract: A single crystal semiconductor separated from a single crystal semiconductor substrate is formed partly over a supporting substrate with a buffer layer provided therebetween. The single crystal semiconductor is separated from the single crystal semiconductor substrate by irradiation with accelerated ions, formation of a fragile layer by the ion irradiation, and heat treatment. A non-single crystal semiconductor layer is formed over the single crystal semiconductor and irradiated with a laser beam to be crystallized, whereby an SOI substrate is manufactured.

Abstract: A method of forming a low-k dielectric layer or film includes forming a porous low-k dielectric layer or film over a wafer or substrate. Active bonding is introduced into the porous low-k dielectric layer or film to improve damage resistance and chemical integrity of the layer or film, to retain the low dielectric constant of the layer and film after subsequent processing. Introduction of the active bonding may be accomplished by introducing OH and/or H radicals into pores of the porous low-k dielectric layer or film to generate, in the case of a Si based low-k dielectric layer or film, Si—OH and/or Si—H active bonds. After further processing of the low-k dielectric film, the active bonding is removed from the low-k dielectric layer or film.

Abstract: A frequency mistuned integrally bladed rotor (IBR) for a gas turbine engine comprises a hub and a circumferential row of blades of varying frequency projecting integrally from the hub. Each blade in the row alternate with another blade having a different pressure surface definition but similar suction surface, leading edge and trailing edge definitions.

Abstract: A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.

Abstract: Methods are generally provided for forming a conductive oxide layer on a substrate. In one particular embodiment, the method can include sputtering a transparent conductive oxide layer on a substrate from a target (e.g., including cadmium stannate) in a sputtering atmosphere comprising cadmium. The transparent conductive oxide layer can be sputtered at a sputtering temperature of about 100° C. to about 600° C. Methods are also generally provided for manufacturing a cadmium telluride based thin film photovoltaic device.

Abstract: It is an object to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide. The method for manufacturing a semiconductor device includes the steps of performing carbonization treatment on a surface of a silicon substrate to form a silicon carbide layer; adding ions to the silicon substrate to form an embrittlement region in the silicon substrate; bonding the silicon substrate and a base substrate with insulating layers interposed between the silicon substrate and the base substrate; heating the silicon substrate and separating the silicon substrate at the embrittlement region to form a stacked layer of the silicon carbide layer and a silicon layer over the base substrate with the insulating layers interposed between the base substrate and the stacked layer; and removing the silicon layer to expose a surface of the silicon carbide layer.