Abstract: Embodiments of the present disclosure provide a method for starting a computing device, a computing device, and a program product. The method includes: acquiring type information on a plurality of host bus adapter (HBA) cards of the computing device; determining a first group of HBA cards in the plurality of HBA cards based on the type information; and starting an operating system of the computing device by preventing scanning of disks connected to the first group of HBA cards. In this way, the number of storage apparatuses that need to be scanned before starting the operating system is reduced, and the starting of the operating system of the computing device is accelerated.

Abstract: Attachment of a pluggable module to an externally-accessible slot of a base unit of a server is detected. The module is configured to execute a first network function of a radio-based communication network. In response to a determination that the module satisfies a security criterion, a second network function is launched. The second network function performs one or more computations on output of the first network function. The output of the first network function is generated at the module in response to a message from a user equipment device of a radio-based communication network.

Abstract: Examples include techniques for an in-network acceleration of a parallel prefix-scan operation. Examples include configuring registers of a node included in a plurality of nodes on a same semiconductor package. The registers to be configured responsive to receiving an instruction that indicates a logical tree to map to a network topology that includes the node. The instruction associated with a prefix-scan operation to be executed by at least a portion of the plurality of nodes.

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: An electronic device may include at least one control unit and an interface or a group of peripheral devices. The group of peripheral devices may include a plurality of peripheral devices (e.g., an input module, a sound output module, a display module, an audio module, a haptic module, a sensor module, a camera module, a power management module, and a communication module). The electronic device includes a plurality of peripheral devices and at least one processor connected to the plurality of peripheral devices via a serial interface, wherein the at least one processor may be configured to control the electronic device to continuously transmit, via the serial interface, a single command frame including a single serial control command, and data frames to be delivered to at least two peripheral devices among the plurality of peripheral devices.

Abstract: A method of transmitting a data packet from a first data processing device toward a second data processing device, the first and second data processing devices being communicably connectable to one another via respective first and second interface devices and over an optical network includes determining a communication path in the optical network to communicably connect the first data processing device to the second data processing device, accessing, by a coordination module communicably connected to the first interface device, a pre-determined training sequence, transmitting, by the coordination module and over the communication path, the pre-determined training sequence to cause the second interface device to recover a signal clock from the pre-determined training sequence and transmitting, by the first data processing device, the data packet toward the second processing device over the communication path. A coordination module implements the method in a computing unit.

Abstract: A device for a vehicle may include a first wireline interface configured to receive a first data stream from a first sensor having a first sensor type for perceiving a surrounding of the vehicle, the first data stream including raw sensor data detected by the first sensor; a second wireline interface configured to receive a second data stream from a second sensor having a second sensor type for perceiving the surrounding of the vehicle, the second data stream including raw sensor data detected by the second sensor; one or more processors configured to generate a coded packet including the received first data stream and the received second data stream by employing vector packet coding on the first data stream and the second data stream; and an output wireline interface configured to transmit the generated coded packet to one or more target units of the vehicle.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

Abstract: A method of providing data communication between a first device and a second device includes, establishing a first communication link with a downstream device connected to the second device using a first mode via a USB-type interface, wherein in the first mode the USB-type interface utilizes a first set of USB communication lanes; establishing a second communication link with the first device via the USB-C port using an Alternate mode wherein the Alt-mode utilizes the first set of USB communication lanes; and, in accordance with establishing the second communication link, changing a mode of the first communication link so that the first communication link does not communicate via the first set of USB communication lanes.

Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.

Abstract: Example implementations relate to executing a workload in a computing system including processing devices, memory devices, and a circuit switch. An example includes identifying first and second instruction-level portions to be consecutively executed by the computing system; determining a first subset of processing devices and a first subset of memory devices to be used to execute the first instruction-level portion; controlling the circuit switch to interconnect the first subset of processing devices and the first subset of memory devices during execution of the first instruction-level portion; determining a second subset of the processing devices and a second subset of the memory devices to be used to execute the second instruction-level portion; and controlling the circuit switch to interconnect the second subset of processing devices and the second subset of memory devices during execution of the second instruction-level portion.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: The invention provides an interface conversion device including a USB connector, a DP connector, a first physical layer (PHY) circuit, a second PHY circuit, a digital buffer, a USB controller, and a path switching circuit. A first terminal of the first PHY circuit is coupled to the USB connector. The digital buffer and the USB controller are coupled to a second terminal of the first PHY circuit. A first terminal of the second PHY circuit is coupled to the DP connector. The path switching circuit selectively electrically connects a second terminal of the second PHY circuit to an output terminal of the digital buffer when the interface conversion device is operated in DP ALT mode. The path switching circuit selectively electrically connects the second terminal of the second PHY circuit to a DP output terminal of the USB controller when the interface conversion device is operated in tunneling mode.

Abstract: A method includes receiving, by a storage unit of a storage network, a check request message from a computing device of the storage network, where the check request message includes a group of slice names of a plurality of sets of slice names associated with a plurality of sets of encoded data slices, where a plurality of data segments are dispersed storage error encoded into the plurality of sets of encoded data slices. The method further includes determining, by the storage unit, whether an error condition exists for an encoded data slice associated with the group of slice names. When no, the method includes sending, by the storage unit, a check response message to the computing device, where the check response message includes a group of slice information regarding the group of slice names. When yes, the method includes disregarding sending the check response message.

Abstract: Framework for controlling passthrough mode is disclosed herein. Exemplary passthrough apparatus may include a relay, a first connection interface connectable to a first universal serial bus (USB) host device, a second connection interface connectable to a USB client device, and a third connection interface connectable to a second USB host device. The passthrough apparatus may further include a housing enclosing the relay and the first, second and third connection interfaces, wherein the relay communicatively couples the second connection interface and the third connection interface while communicatively decoupling the second connection interface and the first connection interface in response to disconnection of power to the relay during a passthrough mode.