Patents Examined by Aurangzeb Hassan
  • Patent number: 11513928
    Abstract: A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 29, 2022
    Assignee: Dell Products L.P.
    Inventors: Andrew Thomas Sultenfuss, Richard Christopher Thompson, Adolfo S. Montero
  • Patent number: 11507522
    Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 22, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sooraj Puthoor, Kishore Punniyamurthy, Onur Kayiran, Xianwei Zhang, Yasuko Eckert, Johnathan Alsop, Bradford Michael Beckmann
  • Patent number: 11494277
    Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is riot limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Timothy Mowry Hollis
  • Patent number: 11494478
    Abstract: Provided are USB connector-free device and method, the device comprising: a host computer 10; a mobile device 20; and an ultra-high-speed module 30, wherein the host computer 10 comprises a USB module, the mobile device (20) comprises: a mobile device USB module (21) connected to the USB module of the host computer (10); mobile device hardware (22) matching with a hardware layer of the mobile device USB module (21); and a mobile device RF module (23) wirelessly matching with the mobile device hardware (22), and the ultra-high-speed module (30) comprises: an ultra-high-speed RF module (31) wirelessly communicating with the mobile device RF module (23); ultra-high-speed module hardware (32) matching with the ultra-high-speed RF module (31) by hardware; and a memory module (33) performing wire-communication with the ultra-high-speed module hardware (32).
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: November 8, 2022
    Assignee: GLS CO., LTD.
    Inventors: Ki-Chan Eun, Ki-Dong Song
  • Patent number: 11486920
    Abstract: Systems, methods, and devices for monitoring operation of industrial equipment are disclosed. In one embodiment, a monitoring system is provided that includes a passive backplane and one more functional circuits that can couple to the backplane. Each of the functional circuits that are coupled to the backplane can have access to all data that is delivered to the backplane. Therefore, resources (e.g., computing power, or other functionality) from each functional circuits can be shared by all active functional circuits that are coupled to the backplane. Because resources from each of the functional circuits can be shared, and because the functional circuits can be detachably coupled to the backplane, performance of the monitoring systems can be tailored to specific applications. For example, processing power can be increased by coupling additional processing circuits to the backplane.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 1, 2022
    Assignee: Bently Nevada, LLC
    Inventors: Michael Alan Tart, Steven Thomas Clemens, Dustin Hess, Paul Richetta
  • Patent number: 11481350
    Abstract: Network chip utility is improved using multi-core architectures with auxiliary wiring between cores to permit cores to utilize components from otherwise inactive cores. The architectures permit, among other advantages, the re-purposing of functional components that reside in defective or otherwise non-functional cores. For instance, a four-core network chip with certain defects in three or even four cores could still, through operation of the techniques described herein, be utilized in a two or even three-core capacity. In an embodiment, the auxiliary wiring may be used to redirect data from a Serializer/Deserializer (“SerDes”) block of a first core to packet-switching logic on a second core, and vice-versa. In an embodiment, the auxiliary wiring may be utilized to circumvent defective components in the packet-switching logic itself. In an embodiment, a core may utilize buffer memories, forwarding tables, or other resources from other cores instead of or in addition to its own.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 25, 2022
    Assignee: Innovium, Inc.
    Inventors: Srinivas Gangam, Ajit Kumar Jain, Anurag Kumar Jain, Avinash Gyanendra Mani, Mohammad Kamel Issa
  • Patent number: 11467995
    Abstract: Methods, systems, and devices for pin mapping for memory devices are described. An apparatus may include a memory array, a plurality of pins, a selector, and a mapping component. The memory array may include a plurality of data lines coupled with a plurality of memory cells. The mapping component may be configured to map a set of data lines to a first set of pins when the selector reflects a first state and to a second set of pins when the selector reflects a second state. The first and second set of pins may have a same quantity of pins. The second set of pins may include pins that are otherwise unused in the second state. The mapping component may be configured to selectively couple unused pins to a fixed potential.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: William A. Lendvay, Scott R. Cyr
  • Patent number: 11442553
    Abstract: The invention relates to a method and an apparatus with circuitry comprising at least one mechanical switch serving to open and/or close an electric contact and a processor unit serving to perform first query and a second query of a contact state of the contact, with the processor unit further serving to provide an output signal on the basis of information on a change of the contact state of the contact detected by means of the first and second queries, wherein the processor unit is configured to perform the second query after the first query with a timing so that the second query precedes an expected bounce of the contact.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: September 13, 2022
    Assignee: CHERRY GMBH
    Inventor: Erwin Koeferl
  • Patent number: 11442880
    Abstract: A storage drive adapter may comprise an adapter board, which may include a first and second carrier module interface to removably engage with a first and a second storage drive carrier module, respectively. The adapter board may further include a dual ported storage drive connector to engage with a complementary storage drive bay interface. The dual ported storage drive connector may include a first port to provide a first signal path from the complementary storage drive bay interface to the first carrier module interface. Similarly, the dual ported storage drive connector may also include a second port to provide a second signal path from the complementary storage drive bay interface to the second carrier module interface.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: September 13, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Andrew Potter, Michael S. Bunker, Timothy A. McCree, Troy Anthony Della Fiora
  • Patent number: 11435811
    Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Roya Baghi, Erica M. Gove, Zahra Hosseinimakarem, Cheryl M. O'Donnell
  • Patent number: 11428737
    Abstract: An IC includes an array of processor units, arranged in two or more subarrays. A subarray has a test generator, a multiplexer to apply a test vector to a datapath, and a test result output. It includes one or more processor units. A test result compressor is coupled with an output of the datapath, and compresses output data to obtain a test signature, which it stores in a signature register. The signature register is legible from outside the subarray. The datapath includes one or more memories and one or more ALUs. Test data travels through the full datapath, including the memories and the ALUs. ALU control registers are overridden during test to ensure a testable datapath.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: August 30, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Thomas Alan Ziaja, Dinesh Rajasavari Amirtharaj
  • Patent number: 11423861
    Abstract: A method includes sorting a plurality of scanning time lengths of the plurality of transmission ports in an ascending order, generating a scanning priority table after the plurality of scanning time lengths of the plurality of transmission ports are sorted, and scanning at least two transmission ports according to the scanning priority table. A transmission port with a higher priority has a shorter scanning time length. A transmission port with a lower priority has a longer scanning time length.
    Type: Grant
    Filed: January 5, 2020
    Date of Patent: August 23, 2022
    Assignee: Qisda Corporation
    Inventors: Jen-Hao Liao, Tse-Wei Fan
  • Patent number: 11416425
    Abstract: A memory includes: a first data bus; a second data bus; and a plurality of bank groups. The bank groups output read data by alternately using the first data bus and the second data bus during read operations of the bank groups. One of the plurality of bank groups transfer read data to the first data bus during a read operation based on an odd-numbered read command. Further, one of the plurality of bank groups transfer transfer one of the plurality of bank groups read data to the second data bus during a read operation based on an even-numbered read command.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong-Uk Lee
  • Patent number: 11409682
    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: August 9, 2022
    Assignee: Rambus Inc.
    Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
  • Patent number: 11397698
    Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: July 26, 2022
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Sun Young Lim, Indong Kim, Jangseok Choi, Craig Hanson
  • Patent number: 11386021
    Abstract: A data packer forma bit stream for forwarding values to memory. The bit stream includes the values and respective prefixes for identifying the values and the data packer is configured to insert the prefixes at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by a preceding prefix. A data unpacker unpacks a bit stream that comprises values and respective prefixes for identifying those values that are located at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by a preceding prefix. The data unpacker identifies a prefix at a predetermined boundary in the bit stream and determine, in dependence on that prefix and the predetermined boundaries, a location of the next prefix in the bit stream.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: July 12, 2022
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: James Andrew Hutchinson, Thomas Oscar Miller, Stephen John Barlow, Jack Stuart Haughton
  • Patent number: 11379399
    Abstract: Example implementations relate to route demultiplexed signal pairs. In some examples, a motherboard of a computing device can include a chipset, a first Peripheral Component Interconnect Express (PCIe) bus, a second PCIe bus, a riser slot, and a demultiplexer connected to the chipset to selectively route particular signal pairs from the chipset to at least one of the first PCIe bus, the second PCIe bus, and the riser slot based on whether a riser card is connected to the riser slot.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 5, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mengistu Taye, Evan Lu
  • Patent number: 11379127
    Abstract: One embodiment provides a computer system. The computer system comprises: a plurality of storage devices; and a first component functioning both as a network interface card and as an access switch, wherein the first component is configured to manage connections to the plurality of storage devices. A respective storage device comprises: an Ethernet port coupled to the first component; at least one microprocessor; a plurality of PCIe lanes; and a plurality of storage drives with non-volatile memory.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: July 5, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11379397
    Abstract: A transmission device capable of control feedback comprises a sender and a receiver. The sender electrically connects to an electronic device through USB type-C for receiving an image signal and sending a control signal. A first processing circuit of the sender converts a network packet into the control signal. A first communication circuit of the sender receives the network packet and sends the image signal. The receiver electrically connects to a display device for sending the image signal and receiving the control signal. A second processing circuit of the receiver encapsulates control signal into the network packet. A second communication circuit of the receiver communicably connects to the first communication circuit to send the network packet and receive the image signal.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 5, 2022
    Assignee: AVER INFORMATION INC.
    Inventors: Han-Yen Chang, Ming Kang Chuang
  • Patent number: 11355165
    Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John David Porter, Suryanarayana B. Tatapudi