Abstract: In some examples, an apparatus for processing a composite signal transmitted uses a first communication protocol via a first port comprising a first connector type, in which the apparatus comprises a processor configured to execute one or more instructions stored in a memory of the apparatus, whereby to cause the apparatus to isolate multiple components of the composite signal received at a first port of the apparatus, the first port of the apparatus, whereby to generate a first and second set of signal components, process at least one component from the second set of signal components to generate a converted signal component, transmit the first set of signal components and the converted signal component from a second port of the apparatus using a second communication protocol, and receive a power supply signal over the second port of the apparatus.

Abstract: A fault-tolerant quantum computer using topological codes such as surface codes can have an architecture that reduces the amount of idle volume generated. The architecture can include qubit modules that generate surface code patches for different qubits and a network of interconnections between different qubit modules. The interconnections can include “port” connections that selectably enable coupling of boundaries of surface code patches generated in different qubit modules and/or “quickswap” connections that selectably enable transferring the state of a surface code patch from one qubit module to another. Port and/or quickswap connections can be made between a subset of qubit modules. For instance port connections can connect a given qubit module to other qubit modules within a fixed range. Quickswap connections can provide a log-tree network of direct connections between qubit modules.

Abstract: In one embodiment, a method includes receiving a token indicating a data chunk becomes available in a first circular buffer of a pre-determined size from a direct memory access component, determining that a computation is to be performed with data including the data chunk based on the token, and generating one or more addresses corresponding to one or more data chunks within the first circular buffer that are to be retrieved for the computation, where a generated address is subtracted by the pre-determined size of the first circular buffer when the generated address is greater than a pre-determined maximum associated with the first circular buffer, and where the generated address is added by the pre-determined size of the first circular buffer when the generated address is less than a pre-determined minimum associated with the first circular buffer.

Abstract: An apparatus may comprise multiplexing circuitry to select an ingress lane from among a plurality of ingress lanes to couple to an egress lane; and retiming circuitry to retime a signal received on the selected ingress lane and transmit the retimed signal on the egress lane.

Abstract: A method and system according to embodiments enable generalized program to program interoperability. The method and system employ an automatic or substantially automatic transform adapter for using a given exchange standard for two-way communication with a program. In order for the adapter to employ the exchange standard, a discovery manager may learn the program's data communications structure and/or format, and may learn data meaning information from the program. An adapter creator may derive a transform which converts the program's data communications structure and data meaning into the exchange standard. The transform may be used by the adapter to enable two-way communication with any adapter and/or program similarly employing the given exchange standard to achieve interoperability.

Abstract: A method includes sending, from the master controller to the slave controller, a follow up message in response to a pull of a predefined pin, wherein the follow up message includes a global time of the master controller when the predefined pin was pulled; sending, from the slave controller to the master controller, a validation message in response to the received follow up message, wherein the validation message includes a global time of the slave controller when the pull of the predefined pin is detected by the slave controller; and validating the time synchronization by checking, at the master controller and/or the slave controller, if a difference between the global time of the master controller when the predefined pin was pulled and the global time of the slave controller when the pull of the predefined pin is detected by the slave controller is smaller than a predefined first threshold.

Abstract: A series circuit and a computing device include a power supply terminal for providing voltage for a plurality of chips disposed on the computing device; a ground terminal disposed at one end of each of the plurality of chips relative to the power supply terminal; and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series, wherein a communication line is connected between adjacent chips of the first predetermined number of chips, a portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a third connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: An exemplary data fabric device comprises a first traffic moderator configured to receive traffic destined for a specific endpoint accessible via a plurality of data paths and divert the traffic from a first data path included in the data paths to a second data path included in the data paths. The exemplary data fabric device also comprises a first interconnect controller that resides within the second data path and is configured to forward the traffic to the specific endpoint via a first communication link to test a functionality of the first communication link. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A driver device of a data interface includes an input/output (I/O) interface, a power interface, a transmitter circuit, and a switching unit. The I/O interface is configured to couple to a load device. The power interface is configured to provide a power supply for transmitting data via the I/O interface. The transmitter circuit is coupled to the I/O interface and to the power interface and is configured to be powered by the power supply and provide an output signal to the load device via the I/O interface in a transmitter mode. The switching unit is coupled to the power interface and is configured to switch off the power interface for the transmitter circuit when the transmitter circuit is operating in a low power state. The transmitter circuit has a power consumption level below a threshold power level in the low power state.

Abstract: Technology related to broadcast packet direct memory access (DMA) operations is disclosed. When a network interface controller (NIC) connected to a host computer receives a broadcast packet, it can transmit a request to an agent process running on the host computer for a plurality of destination buffers. In some embodiments, the request to the agent comprises all or part of the packet, or metadata about the packet. In such embodiments, the agent can use the contents of the request to identify services that should receive the packet. Alternatively, the NIC can identify the destination services and can transmit identifiers for the destination services to the agent. The agent can transmit requests for memory buffers to the services and can receive memory location identifiers in response. The agent can transmit the identifiers to the NIC, which can perform multiple DMA operations to write the broadcast packet to the identified memory locations.

Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

Abstract: An accessory and an electronic device capable of suppressing malfunction and failure of the accessory when a command to be executed by the accessory is transmitted from the electronic device to the accessory and reducing the memory capacity. The accessory is communicably connected to the electronic device. The accessory includes a communication unit that communicates with the electronic device, a storage unit that allows reading therefrom and writing therein and stores a flag indicating whether execution of a command by the accessory is allowed or not, a control unit that, upon receipt of a predetermined command from the electronic device, does not execute the predetermined command in a case where the flag indicates that execution of the command is not allowed, and executes the predetermined command in a case where execution of the command is allowed.

Abstract: Handshake controller and handshake control method for one or more charging protocols. For example, a handshake controller for one or more charging protocols includes: a port detection unit connected to a plurality of USB ports and configured to generate a detection signal; a port selection unit configured to receive the detection signal and connected to the plurality of USB ports; an interface unit connected to the port selection unit; and a digital handshake unit connected to the interface unit; wherein the port detection unit is further configured to: determine whether a single USB port of the plurality of USB ports is connected to a load device.

Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.

Abstract: In one embodiment, an apparatus includes a port to transmit and receive data over a link; and protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol (e.g., PCIe or CXL) across the link. The protocol stack circuitry constructs memory write request transaction layer packets (TLPs) for memory write transactions, wherein fields of the memory write request TLPs indicate a virtual channel (VC) other than VC0, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction. The memory write request TLP is transmitted over the link and a completion TLP is received over the link in response, indicating a completion for the memory write request TLP.

Abstract: This application discloses a charging cable-based data transmission method and an electronic device. A first electronic device is connected to a second electronic device through a third electronic device, and the third electronic device includes a first data signal line and a second data signal line. When the method is applied to the first electronic device, the first electronic device may detect a connection to the second electronic device; send a first message through a first pin, where the first pin is connected to the first data signal line; and receive a second message through a second pin, where the second pin is connected to the second data signal line, and the first message and the second message are used for charging setting of the first electronic device.

Abstract: In some embodiments, a system for communicating USB information via a non-USB extension medium is provided. The system comprises a downstream facing port device (DFP device). The DFP device is configured to receive, via the non-USB extension medium, an ACK IN packet addressed to a first endpoint while receiving DATA packets from a second endpoint. The DFP device is further configured to detect an end of transmission of the DATA packets from the second endpoint; determine a number of packets that can be received from the first endpoint during a remaining amount of time in a current bus interval; and transmit at least one synthetic ACK IN packet to the first endpoint based on the number of packets.

Abstract: Techniques are provided for creating secure IO (input/output) user connections between IO users and storage volumes. One method comprises establishing an IO user connection between a processor-based IO user and at least a portion of a storage volume on a storage array; obtaining IO user context information associated with the IO user connection, wherein the IO user context information comprises one or more keys for signature verification; and transmitting one or more IO operations over the IO user connection, wherein a signature associated with a given IO operation is evaluated to verify that the signature is a valid signature of one or more of the processor-based IO user and the storage array. The obtained IO user context information may further comprise an identifier of a signature generation function that generates the signature associated with the given IO operation and a connection identity string identifying the IO user connection.

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: An interface bridging device (“IBD”) capable of facilitating data conversion between data streams of D physical layer (“D-PHY”) and data streams of C physical layer (“C-PHY”) is disclosed. IBD includes a first integrated circuit (“IC”) component, a bridge component, and a second IC component. The first IC component is able to process digital information and is configured to generate a first data stream formatted in D-PHY data stream. The bridge component receives the first data via a D-PHY bus and subsequently converts the first data stream to a second data stream formatted in a C-PHY data stream. The second IC component is configured to obtain the second data stream via a C-PHY bus.