Patents Examined by Aurangzeb Hassan
  • Patent number: 11073990
    Abstract: A data storage device includes a memory used to store device identification information, wherein the data storage device is operable to communication with an electronic device to receive the device identification information sent from the electronic device and to store the device identification information in the memory, and wherein the data storage device is operable to provide a hardware-switching device with the device identification information from the memory. A method for identifying multiple electronic devices includes providing, for each electronic device, a corresponding data storage device communicating with a hardware-switching device and storing device identification information related to each electronic device in the corresponding data storage device.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 27, 2021
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Zhaoli Wang, Qian QiaoNeng, CheKim Chhuor, Weiyi Xie, Tang WenWei
  • Patent number: 11074580
    Abstract: A method and device for retrofitting a machine controller to accommodate one or more electronic peripheral devices is disclosed herein. A device with processor(s), memory, a slave interface, and host interface(s) performs as a virtual peripheral by registering itself as a slave to the machine controller coupled with the slave interface and performs as a virtual machine controller by registering peripheral(s) coupled with the host interface(s) as slaves to the device. The device receives a command from the machine controller via the slave interface and, in response to receiving the command: sends an acknowledgement to the machine controller via the slave interface; and relays the command to a respective peripheral via a respective one of the host interface(s), where the device sends signals to and from the machine controller asynchronous of sending signals to and from the peripheral(s).
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 27, 2021
    Assignee: PAYRANGE INC.
    Inventor: Paresh K. Patel
  • Patent number: 11074210
    Abstract: Circuits, methods, and apparatus that can allow chipsets in an electronic device to share information such that they can more efficiently utilize resources that are available in the electronic device. One example can provide a bus that is shared by three or more chipsets in an electronic device. This shared bus can be used by the chipsets in the electronic device to communicate and negotiate for the utilization of resources of the electronic device.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 27, 2021
    Assignee: Apple Inc.
    Inventors: Farouk Belghoul, Paul V. Flynn, Tideya Kella, Vijay Kumar Ramamurthi
  • Patent number: 11055242
    Abstract: Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 6, 2021
    Assignee: ATI Technologies ULC
    Inventors: Gordon Caruk, Jaroslaw Marczewski
  • Patent number: 11055246
    Abstract: The present disclosure is directed to an input/output module.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 6, 2021
    Assignee: Bedrock Automation Platforms Inc.
    Inventors: Craig Markovic, Albert Rooyakkers, James G. Calvin
  • Patent number: 11048420
    Abstract: At the start of an I/O cutover process that changes host computer access to a logical volume from a source data storage appliance to a destination data storage appliance, and during which processing of host I/O operations directed to the logical volume is frozen, at least one I/O freeze timer is set. In response to expiration of the I/O freeze timer, and prior to completion of the I/O cutover process, processing of host I/O operations directed to the logical volume is resumed.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 29, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Dmitry Tylik, Matthew H. Long, Jean M. Schiff, Yuri A. Stotski, Anil K. Koluguri
  • Patent number: 11036649
    Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 15, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Ravikiran Kaidala Lakshman, Tanjore K. Suresh, Deepak Srinivas Mayya, Sagar Borikar
  • Patent number: 11023258
    Abstract: Dynamically configurable server platforms and associated apparatus and methods. A server platform including a plurality of CPUs installed in respective sockets may be dynamically configured as multiple single-socket servers and as a multi-socket server. The CPUs are connected to a platform manager component comprising an SoC including one or more processors and an embedded FPGA. Following a platform reset, an FPGA image is loaded, dynamically configuring functional blocks and interfaces on the platform manager. The platform manager also includes pre-defined functional blocks and interfaces. During platform initialization the dynamically-configured functional blocks and interfaces are used to initialize the server platform, while both the pre-defined and dynamically-configured functional blocks and interfaces are used to support run-time operations.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Neeraj S. Upasani, Jeanne Guillory, Wojciech Powiertowski, Sergiu D Ghetie, Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 11023406
    Abstract: Information maintained in a port control block of an embedded port of a host bus adapter is stored in a host bus adapter memory, wherein the information corresponds to login attributes and state data of remote ports. In response to storing the information in the host bus adapter memory, code in the embedded port is updated. In response to the updating of the code in the embedded port, the stored information is restored from the host bus adapter memory to the port control block of the embedded port.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger G. Hathorn, Steven E. Klein, Mikel W. Welsh
  • Patent number: 11016920
    Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava
  • Patent number: 11016781
    Abstract: Some example embodiments presented herein provide methods and memory modules for configuring vendor-specific registers in the memory modules to enable and/or disable vendor-specific functionality. The vendor-specific register space may be organized by a vendor-specific logic and accessed by a standard memory access command received while the memory is in a programming mode. A write command may be received from a host device to switch the memory module to a programming mode, and the memory module may be switched to the programming mode responsive to the command. A memory write command may be received from the host device involving the memory module switched to the programming mode, and a vendor-specific register may be configured based on the memory write command and the organization of the vendor-specific register indicated by the vendor-specific logic.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eldho Pathiyakkara Thombra Mathew, Yash Jajoo, Jai Babu Mahankud, Hari Babu Chimakurthy
  • Patent number: 11010327
    Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 18, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sharon Graif, Meital Zangvil, Lior Amarilio
  • Patent number: 11010325
    Abstract: An adapter includes a first coupling component and a second coupling component to establish bidirectional communications between two processing devices by passing data signals through a memory card slot on one of the devices. The adapter includes a first coupling interface configured to couple with the memory card slot on a first one of the two processing devices and further includes a second coupling interface configured to couple with a second processing device. The second coupling interface is of a different form factor than the first coupling interface.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Adam Nelson Swett, Vlad Radu Calugaru
  • Patent number: 10997022
    Abstract: A method includes receiving, by a storage unit of a set of storage units of a storage network, a write request of a set of write requests that includes a first group of slice payloads for first encoded data slices of each set of a plurality of sets of encoded data slices and a corresponding revision level. The method includes processing, by the storage unit, the write request by determining whether the corresponding revision level of each of the first encoded data slices is a next revision level and generating a write response message that includes a group of status messages for the first encoded data slices based on the determining whether the corresponding revision level of each of the first encoded data slices is the next revision level. The method continues by sending the write response message to a computing device of the storage network.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 4, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 10996879
    Abstract: An apparatus in one embodiment comprises a host device configured to communicate over a network with a storage system. The host device comprises a plurality of nodes each comprising a plurality of processing devices and at least one communication adapter. The host device further comprises a multi-path input-output (MPIO) driver that is configured to obtain an input-output (IO) operation that targets a given logical volume and to identify a source node for the IO operation. The MPIO driver identifies a plurality of paths between the source node and the given logical volume via the communication adapters of the plurality of nodes and determines locality information for each identified path. The MPIO driver is further configured to select a target path from the identified paths based at least in part on the determined locality information and to deliver the obtained IO operation to the given logical volume via the selected target path.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 4, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: Kurumurthy Gokam
  • Patent number: 10997090
    Abstract: Techniques are disclosed for enabling an integrated sensor hub of a main computer to access a detachable peripheral device. In an embodiment, a system includes a main unit having a peripheral interface, an embedded controller, and a device controller. The peripheral interface is configured to be detachably coupled to a peripheral. The peripheral includes a control unit and an input/output device. The embedded controller is configured to communicate with the control unit of the peripheral via the peripheral interface while the peripheral is attached to the peripheral interface. The embedded controller includes at least one data register, and in some embodiments, a set of data registers, configured to store data relating to the peripheral and to the corresponding input/output device. The device controller is configured to read data from the data register(s) of the embedded controller, write data to the data register(s) of the embedded controller, or both.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Guangyu Ren, Kun-Feng Lin, Ke Han
  • Patent number: 10983936
    Abstract: A programmable arbitrary sequence direct memory access (DMA) controller accesses sequentially addressed memory locations (source or destination) using address pointer registers. Each sequentially addressed memory location containing an indirect memory address is stored in an address latch and used to access the actual non-sequential memory location to be accessed by the DMA transfer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: April 20, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Keith Edwin Curtis
  • Patent number: 10977203
    Abstract: A data transmission method and an apparatus used in a virtual switch technology are provided. An IO request of a virtual machine VM for accessing a file or a disk is received. When the IO request is to be sent to a physical NIC by using a user mode Open vSwitch (OVS), the IO request is converted into an Internet Small Computer Systems Interface (iSCSI) command in a user mode The iSCSI command is then sent to the user mode OVS. The user mode OVS sends the iSCSI command to the physical NIC.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 13, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ming Zhang, Lina Lu
  • Patent number: 10977202
    Abstract: An adaptable connector, a non-standard PCIe module, and a computer readable medium are disclosed. The adaptable connector for a PCIe interface allows for multiple standard PCIe modules and non-standard PCIe modules at different times An external I/O port has a set of non-PCIe I/O signal lanes coupled to the adaptable connector in lieu of a set of root port host PCIe signal lanes when a non-standard PCIe module is mated to the adaptable connector.
    Type: Grant
    Filed: January 28, 2017
    Date of Patent: April 13, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Seiler, Justin Barth, Mark Lessman
  • Patent number: 10928440
    Abstract: Systems, methods, and devices for monitoring operation of industrial equipment are disclosed. In one embodiment, a monitoring system is provided that includes a passive backplane and one more functional circuits that can couple to the backplane. Each of the functional circuits that are coupled to the backplane can have access to all data that is delivered to the backplane. Therefore, resources (e.g., computing power, or other functionality) from each functional circuits can be shared by all active functional circuits that are coupled to the backplane. Because resources from each of the functional circuits can be shared, and because the functional circuits can be detachably coupled to the backplane, performance of the monitoring systems can be tailored to specific applications. For example, processing power can be increased by coupling additional processing circuits to the backplane.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 23, 2021
    Assignee: BENTLY NEVADA, LLC
    Inventors: Michael Alan Tart, Steven Thomas Clemens, Dustin Hess, Paul Richetta