Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.

Abstract: In one embodiment, an apparatus includes a port to transmit and receive data over a link; and protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol (e.g., PCIe or CXL) across the link. The protocol stack circuitry constructs memory write request transaction layer packets (TLPs) for memory write transactions, wherein fields of the memory write request TLPs indicate a virtual channel (VC) other than VC0, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction. The memory write request TLP is transmitted over the link and a completion TLP is received over the link in response, indicating a completion for the memory write request TLP.

Abstract: In some embodiments, a system for communicating USB information via a non-USB extension medium is provided. The system comprises a downstream facing port device (DFP device). The DFP device is configured to receive, via the non-USB extension medium, an ACK IN packet addressed to a first endpoint while receiving DATA packets from a second endpoint. The DFP device is further configured to detect an end of transmission of the DATA packets from the second endpoint; determine a number of packets that can be received from the first endpoint during a remaining amount of time in a current bus interval; and transmit at least one synthetic ACK IN packet to the first endpoint based on the number of packets.

Abstract: Techniques are provided for creating secure IO (input/output) user connections between IO users and storage volumes. One method comprises establishing an IO user connection between a processor-based IO user and at least a portion of a storage volume on a storage array; obtaining IO user context information associated with the IO user connection, wherein the IO user context information comprises one or more keys for signature verification; and transmitting one or more IO operations over the IO user connection, wherein a signature associated with a given IO operation is evaluated to verify that the signature is a valid signature of one or more of the processor-based IO user and the storage array. The obtained IO user context information may further comprise an identifier of a signature generation function that generates the signature associated with the given IO operation and a connection identity string identifying the IO user connection.

Abstract: This application discloses a charging cable-based data transmission method and an electronic device. A first electronic device is connected to a second electronic device through a third electronic device, and the third electronic device includes a first data signal line and a second data signal line. When the method is applied to the first electronic device, the first electronic device may detect a connection to the second electronic device; send a first message through a first pin, where the first pin is connected to the first data signal line; and receive a second message through a second pin, where the second pin is connected to the second data signal line, and the first message and the second message are used for charging setting of the first electronic device.

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: An interface bridging device (“IBD”) capable of facilitating data conversion between data streams of D physical layer (“D-PHY”) and data streams of C physical layer (“C-PHY”) is disclosed. IBD includes a first integrated circuit (“IC”) component, a bridge component, and a second IC component. The first IC component is able to process digital information and is configured to generate a first data stream formatted in D-PHY data stream. The bridge component receives the first data via a D-PHY bus and subsequently converts the first data stream to a second data stream formatted in a C-PHY data stream. The second IC component is configured to obtain the second data stream via a C-PHY bus.

Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.

Abstract: A system includes a multidrop cable and a connector. The connector is configured to couple to one or more MCC withdrawable units installed in one or more respective buckets of an MCC, wherein the connector is configured to couple the one or more MCC withdrawable units to, and decouple the one or more MCC withdrawable units from, the multidrop cable without disrupting a network or a subnet of the MCC.

Abstract: A method and system for uploading data in real time via a USB virtual serial port, and a USB host includes: creating a receiving thread, and presetting a plurality of USB transactions being USB BULK IN packets, and a length requested to be uploaded, submitting the plurality of USB transactions to a USB host driver, and when the receiving thread receives a returned data packet, transmitting the returned data packet to a serial port application layer buffer, immediately applying for a new USB transaction, and submitting the new USB transaction to the USB host driver; and executing, a USB transaction ranked first in a USB transaction queue, when data sent by a USB device is received and the data meets the batch endpoint size, ending the USB transaction and returning a data packet to the receiving thread, and immediately executing next USB transaction in the USB transaction queue.

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A transmission device according to an aspect of the present disclosure communicates with a reception device via a control data bus. The transmission device includes a generation unit that generates an interrupt request, and a transmission section that transmits data to the reception device via the control data bus. The interrupt request includes at least an identification bit to identify a type of transmission data, an information bit for the transmission data, and the transmission data.

Abstract: Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

Abstract: Disclosed herein are systems and techniques for remote bus enable. In some embodiments, a communication system with remote enable functionality may include: a master transceiver coupled to a downstream link of a bus; a voltage regulator, wherein the voltage regulator has a voltage output and an enable input, and the voltage output is coupled to the master transceiver; and a switch coupled to the enable input of the voltage regulator.

Abstract: Embodiments of the present disclosure provide a method for starting a computing device, a computing device, and a program product. The method includes: acquiring type information on a plurality of host bus adapter (HBA) cards of the computing device; determining a first group of HBA cards in the plurality of HBA cards based on the type information; and starting an operating system of the computing device by preventing scanning of disks connected to the first group of HBA cards. In this way, the number of storage apparatuses that need to be scanned before starting the operating system is reduced, and the starting of the operating system of the computing device is accelerated.

Abstract: Attachment of a pluggable module to an externally-accessible slot of a base unit of a server is detected. The module is configured to execute a first network function of a radio-based communication network. In response to a determination that the module satisfies a security criterion, a second network function is launched. The second network function performs one or more computations on output of the first network function. The output of the first network function is generated at the module in response to a message from a user equipment device of a radio-based communication network.

Abstract: Examples include techniques for an in-network acceleration of a parallel prefix-scan operation. Examples include configuring registers of a node included in a plurality of nodes on a same semiconductor package. The registers to be configured responsive to receiving an instruction that indicates a logical tree to map to a network topology that includes the node. The instruction associated with a prefix-scan operation to be executed by at least a portion of the plurality of nodes.

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A device for a vehicle may include a first wireline interface configured to receive a first data stream from a first sensor having a first sensor type for perceiving a surrounding of the vehicle, the first data stream including raw sensor data detected by the first sensor; a second wireline interface configured to receive a second data stream from a second sensor having a second sensor type for perceiving the surrounding of the vehicle, the second data stream including raw sensor data detected by the second sensor; one or more processors configured to generate a coded packet including the received first data stream and the received second data stream by employing vector packet coding on the first data stream and the second data stream; and an output wireline interface configured to transmit the generated coded packet to one or more target units of the vehicle.