Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.

Abstract: An information handling system may include a management controller and information handling resources that are coupled to the management controller via a first communication channel and a second communication channel, each information handling resource having a first communication channel identifier, and each information handling resource having a second communication channel identifier. The management controller may query the information handling resources via the first communication channel to determine a first set of unique identifiers for the information handling resources; query the information handling resources via the second communication channel to determine a second set of unique identifiers for the information handling resources; and based on a comparison between the first set of unique identifiers and the second set of unique identifiers, create a mapping that correlates the first communication channel identifiers with the second communication channel identifiers.

Abstract: An UART interface circuit is provided in the invention. The UART interface circuit is configured in an electronic device. The UART interface circuit includes a baud-rate generating circuit, a control circuit, and a receiving circuit. The baud-rate generating circuit is configured to generate a baud rate and a start-bit cycle. The control circuit obtains the wakeup stable time from the wakeup time circuit of the electronic device and obtains the start-bit cycle from the baud-rate generating circuit. The receiving circuit is configured to capture data from the start bit or the first data bit of UART data. When the electronic device is woken up by the UART data, the control circuit compares the start-bit cycle with the wakeup stable time to direct the receiving circuit to start capturing data from the start bit or the first data bit of the UART data.

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: A setting to be applied at a docking station is obtained, either from a memory of the docking station, or from another device connected to a network by first obtaining, from a user device connected to the docking station, an identity of the user device and/or an identity of a user of the user device. Based on the identity of the user and/or the user device, a configuration set, of a plurality of configuration sets, that identifies at least one setting to be applied at the docking station is obtained and a setting to apply at the docking station is determined based at least partly on the configuration set. The docking station may store a set of docking station specific settings which can be used in conjunction with the setting(s) determined from the configuration set.

Abstract: An adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than either the first interface or the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor.

Abstract: In some embodiments, a system for communicating USB information via a non-USB extension medium is provided. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The DFP device is configured to receive, from the UFP device via the extension medium, a first ACK IN packet addressed to a first endpoint and a second ACK IN packet addressed to a second endpoint after receiving the first ACK IN packet. In response to detecting that the USB-compliant connection is available, the DFP device compares a bInterval value for the first endpoint to a bInterval value for the second endpoint; and in response to determining that the bInterval value for the second endpoint is smaller than the bInterval value for the first endpoint, the DFP device transmits a synthetic ACK IN packet to the second endpoint based on the second ACK IN packet.

Abstract: In accordance with one disclosed method, a client device may be caused to present a user interface for an application, the user interface enabling selective access to a plurality of resources via the client device. A state of a peripheral device that is connectable to the client device may be determined and, based at least in part on the state of the peripheral device, at least a first resource, from among the plurality of resources, may be identified with which the peripheral device can interact. Based at least in part on the identifying of the first resource, the user interface may be caused to include at least a first selectable user interface element that, when selected, causes the client device to access to the first resource so as to enable the peripheral device to interact with the first resource.

Abstract: Methods and systems for managing power distribution and/or mechanical load in data processing systems is provided. The power distribution may be managed using multifunction power buses that may relieve a motherboard of a data processing system from distributing power. The mechanical load may be managed using an adapter plate that may relieve the motherboard of the data processing system from providing for attachment of devices based on the location of the mechanical mounting hardware on the devices. By doing so, motherboards may be standardized and customized for use with various devices.

Abstract: A computing system capable of obtaining a calculation speed exceeding that of 16-bit floating point processing while maintaining accuracy of calculation results. A computing system includes a parameter server, a communication path and a worker. The parameter server has a storage unit that stores a parameter value of a training target model, and a first conversion unit that converts the parameter value into data represented by a floating point number with 10 bits or less. The communication path transmits the data transmitted and received between the parameter server and the worker. The worker has a processing unit that computes a product and a sum of the data. The parameter server further has a second conversion unit that converts the data with 10 bits or less received from the worker into an updating difference, and an updating unit that updates the parameter value on the basis of the updating difference.

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: A method for identifying and pairing a signal transmitting device, including: obtaining a setting value of a master identification key; obtaining a setting value of a slave identification key; determining whether at least one of the setting values equals to an initial value; determining whether the setting value of the master identification key equals to the setting value of the slave identification key when none of the setting values equals to the initial value; and controlling the signal processing device to operate in a limited mode when the setting value of the master identification key and the setting value of the slave identification key are not equal. In the limited mode, a signal processing device does not output any signal to the signal transmitting device or ignores any signal received from a signal transmitting device, or the signal processing device only outputs a limited signal to the signal transmitting device.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, an SPI bus, a memory device electrically connected to the master device via the SPI bus, and a plurality of slave devices electrically connected to the master device via the eSPI bus. Each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line. After obtaining program code from the memory device via the master device, a first slave device is configured to decrypt the program code according to a first security code, and transmit the program code decrypted by the first security code to the slave devices via the control line, so that the program code decrypted by the first security code is decrypted in the slave devices according to a decryption sequence.

Abstract: A current loop includes a receiver assembly and a transmitter assembly. The current loop also includes: a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes: a Highway Addressable Remote Transducer (HART) modem; a component in communication with the HART modem via a partial set of Universal Asynchronous Receiver-Transmitter (UART) communication lines; and a break extension protocol controller coupled to or included with the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the partial set of UART communication lines.

Abstract: A method includes receiving, by a storage unit of a set of storage units of a storage network, a write request regarding an encoded data slice, where the write request includes a slice payload and a corresponding revision level of the encoded data slice. The method further includes determining whether the corresponding revision level of the encoded data slice is a next revision level. The method further includes generating a write response message that includes a status message for the encoded data slice based on the determining whether the corresponding revision level of the encoded data slice is the next revision level, where when the corresponding revision level is the next revision level, the status message includes an operation succeeded message. The method further includes sending the write response message to a computing device of the storage network.

Abstract: The reception module includes a reception buffer that is shared by the first and second transmission modules to store the packet. The first transmission module is configured to: transmit, to the second transmission module, a lending request of the reception buffer allocated to the second transmission module, based on a use amount of the reception buffer allocated to the first transmission module, and increase an allocation amount of the reception buffer for the first transmission module in a case where the second transmission module has transmitted an acceptance response to the lending request. The second transmission module is configured to: receive the lending request and transmit the acceptance response to the first transmission module based on a use amount of the reception buffer allocated to the second transmission module, and decrease an allocation amount of the reception buffer for the second transmission module when transmitting the acceptance response.