Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.

Abstract: A system includes a multidrop cable and a connector. The connector is configured to couple to one or more MCC withdrawable units installed in one or more respective buckets of an MCC, wherein the connector is configured to couple the one or more MCC withdrawable units to, and decouple the one or more MCC withdrawable units from, the multidrop cable without disrupting a network or a subnet of the MCC.

Abstract: A method and system for uploading data in real time via a USB virtual serial port, and a USB host includes: creating a receiving thread, and presetting a plurality of USB transactions being USB BULK IN packets, and a length requested to be uploaded, submitting the plurality of USB transactions to a USB host driver, and when the receiving thread receives a returned data packet, transmitting the returned data packet to a serial port application layer buffer, immediately applying for a new USB transaction, and submitting the new USB transaction to the USB host driver; and executing, a USB transaction ranked first in a USB transaction queue, when data sent by a USB device is received and the data meets the batch endpoint size, ending the USB transaction and returning a data packet to the receiving thread, and immediately executing next USB transaction in the USB transaction queue.

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A transmission device according to an aspect of the present disclosure communicates with a reception device via a control data bus. The transmission device includes a generation unit that generates an interrupt request, and a transmission section that transmits data to the reception device via the control data bus. The interrupt request includes at least an identification bit to identify a type of transmission data, an information bit for the transmission data, and the transmission data.

Abstract: Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

Abstract: Disclosed herein are systems and techniques for remote bus enable. In some embodiments, a communication system with remote enable functionality may include: a master transceiver coupled to a downstream link of a bus; a voltage regulator, wherein the voltage regulator has a voltage output and an enable input, and the voltage output is coupled to the master transceiver; and a switch coupled to the enable input of the voltage regulator.

Abstract: Embodiments of the present disclosure provide a method for starting a computing device, a computing device, and a program product. The method includes: acquiring type information on a plurality of host bus adapter (HBA) cards of the computing device; determining a first group of HBA cards in the plurality of HBA cards based on the type information; and starting an operating system of the computing device by preventing scanning of disks connected to the first group of HBA cards. In this way, the number of storage apparatuses that need to be scanned before starting the operating system is reduced, and the starting of the operating system of the computing device is accelerated.

Abstract: Attachment of a pluggable module to an externally-accessible slot of a base unit of a server is detected. The module is configured to execute a first network function of a radio-based communication network. In response to a determination that the module satisfies a security criterion, a second network function is launched. The second network function performs one or more computations on output of the first network function. The output of the first network function is generated at the module in response to a message from a user equipment device of a radio-based communication network.

Abstract: Examples include techniques for an in-network acceleration of a parallel prefix-scan operation. Examples include configuring registers of a node included in a plurality of nodes on a same semiconductor package. The registers to be configured responsive to receiving an instruction that indicates a logical tree to map to a network topology that includes the node. The instruction associated with a prefix-scan operation to be executed by at least a portion of the plurality of nodes.

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A device for a vehicle may include a first wireline interface configured to receive a first data stream from a first sensor having a first sensor type for perceiving a surrounding of the vehicle, the first data stream including raw sensor data detected by the first sensor; a second wireline interface configured to receive a second data stream from a second sensor having a second sensor type for perceiving the surrounding of the vehicle, the second data stream including raw sensor data detected by the second sensor; one or more processors configured to generate a coded packet including the received first data stream and the received second data stream by employing vector packet coding on the first data stream and the second data stream; and an output wireline interface configured to transmit the generated coded packet to one or more target units of the vehicle.

Abstract: An electronic device may include at least one control unit and an interface or a group of peripheral devices. The group of peripheral devices may include a plurality of peripheral devices (e.g., an input module, a sound output module, a display module, an audio module, a haptic module, a sensor module, a camera module, a power management module, and a communication module). The electronic device includes a plurality of peripheral devices and at least one processor connected to the plurality of peripheral devices via a serial interface, wherein the at least one processor may be configured to control the electronic device to continuously transmit, via the serial interface, a single command frame including a single serial control command, and data frames to be delivered to at least two peripheral devices among the plurality of peripheral devices.

Abstract: A method of transmitting a data packet from a first data processing device toward a second data processing device, the first and second data processing devices being communicably connectable to one another via respective first and second interface devices and over an optical network includes determining a communication path in the optical network to communicably connect the first data processing device to the second data processing device, accessing, by a coordination module communicably connected to the first interface device, a pre-determined training sequence, transmitting, by the coordination module and over the communication path, the pre-determined training sequence to cause the second interface device to recover a signal clock from the pre-determined training sequence and transmitting, by the first data processing device, the data packet toward the second processing device over the communication path. A coordination module implements the method in a computing unit.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

Abstract: A method of providing data communication between a first device and a second device includes, establishing a first communication link with a downstream device connected to the second device using a first mode via a USB-type interface, wherein in the first mode the USB-type interface utilizes a first set of USB communication lanes; establishing a second communication link with the first device via the USB-C port using an Alternate mode wherein the Alt-mode utilizes the first set of USB communication lanes; and, in accordance with establishing the second communication link, changing a mode of the first communication link so that the first communication link does not communicate via the first set of USB communication lanes.

Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.