Abstract: A method includes receiving, by a storage unit of a set of storage units of a storage network, a write request regarding an encoded data slice, where the write request includes a slice payload and a corresponding revision level of the encoded data slice. The method further includes determining whether the corresponding revision level of the encoded data slice is a next revision level. The method further includes generating a write response message that includes a status message for the encoded data slice based on the determining whether the corresponding revision level of the encoded data slice is the next revision level, where when the corresponding revision level is the next revision level, the status message includes an operation succeeded message. The method further includes sending the write response message to a computing device of the storage network.

Abstract: The reception module includes a reception buffer that is shared by the first and second transmission modules to store the packet. The first transmission module is configured to: transmit, to the second transmission module, a lending request of the reception buffer allocated to the second transmission module, based on a use amount of the reception buffer allocated to the first transmission module, and increase an allocation amount of the reception buffer for the first transmission module in a case where the second transmission module has transmitted an acceptance response to the lending request. The second transmission module is configured to: receive the lending request and transmit the acceptance response to the first transmission module based on a use amount of the reception buffer allocated to the second transmission module, and decrease an allocation amount of the reception buffer for the second transmission module when transmitting the acceptance response.

Abstract: A method and system according to embodiments enable generalized program to program interoperability. The method and system employ an automatic or substantially automatic transform adapter for using a given exchange standard for two-way communication with a program. In order for the adapter to employ the exchange standard, a discovery manager may learn the program's data communications structure and/or format, and may learn data meaning information from the program. An adapter creator may derive a transform which converts the program's data communications structure and data meaning into the exchange standard. The transform may be used by the adapter to enable two-way communication with any adapter and/or program similarly employing the given exchange standard to achieve interoperability.

Abstract: A communication device is configured to exchange regular data bidirectionally with counterpart communication device via a regular interface; and to exchange additional data bidirectionally with the counterpart device via an additional interface. The device has a regular pinout corresponding to the regular interface that enables communication of regular data with the counterpart device; and an additional pinout with at least one additional pin, corresponding to the additional interface that enables communication of additional data with the counterpart device. The device has default data handling circuitry communicatively coupled to the additional pin, and configured, in a default mode, to transmit and receive additional default data via the additional pin. The first device has additional function data handling circuitry communicatively coupled to the additional pin and configured, in an active mode, to transmit and receive additional function data via the additional interface.

Abstract: A relay device includes a first connecting unit, a second connecting unit, a first notifying unit, a second notifying unit, and a communicating unit. The first connecting unit is connected with a first interface of a first device, the first interface being not compliant with USB (Universal Serial Bus) standard. The second connecting unit is connected with a second interface of a second device, the second interface being compliant with the USB standard. The first notifying unit notifies the second device that the relay device is a USB device. The second notifying unit notifies the first device that the second device has been connected to the second connecting unit. The communicating unit relays communication carried out between the second device and the first device.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: Examples herein include a computer system and methods. Some computer systems comprise two or more devices (each device comprises at least one processing circuit), where each computing device comprises or is communicatively coupled to one or more optical network interface controller (O-NIC) cards. Each O-NIC card comprises at least two bidirectional optical channels to transmit data and to receive additional data from each O-NIC card communicatively coupled to a device, over a channel. The system also includes one or more interfaces and a memory. Program instructions execute a method on one or more processors in communication with a memory, and the method includes modifying, during runtime of at least one application, a pairing over a given bidirectional optical channel of an interface of the interfaces to a given device.

Abstract: The present invention discloses a series circuit and a computing device, including: a power supply terminal for providing voltage for a plurality of chips disposed on the computing device; a ground terminal disposed at one end of each of the plurality of chips relative to the power supply terminal; and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series, wherein a communication line is connected between adjacent chips of the first predetermined number of chips, a portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a third connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: Systems and method are provided. An illustrative system includes a first compute node having a first processing unit, a first compute node port, and a first peripheral component interconnect bus configured to carry data between the first processing unit and the first compute node port. The system may further include a multi-host network interface controller having a first multi-host port, where the first multi-host port is configured to connect with the first compute node port via a first peripheral component interconnect cable, a network port, where the network port is configured to receive a network interface of a networking cable, and processing circuitry configured to translate and carry data between the first multi-host port and the network port.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A management apparatus (10) includes a request reception unit (111) configured to receive a transmission request for configuration information transmitted from a transmission apparatus (12), together with key information unique to the transmission apparatus (12) and feature information obtained from peripheral information of the transmission apparatus (12), a configuration-information extraction unit (112) configured to extract configuration information corresponding to the key information and the feature information added in the transmission request that is transmitted from the transmission apparatus (12) and received by the request reception unit (111) from a database in which a combination of key information, feature information, and configuration information for each transmission apparatus is registered, and a configuration-information output unit (113) configured to output the configuration information extracted by the configuration-information extraction unit (112) to the transmission apparatus (12) tha

Abstract: An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels.

Abstract: Access to peripherals can be managed in a containerized environment. A management service can be employed on a computing device to detect when a container is created. When a container is created or a peripheral is connected, the management service can determine that an application running within the container should be allowed to access a peripheral. The management service can then interface with a peripheral mapper running within the container to enable the application to access the peripheral. A peripheral access manager can also be employed to isolate the peripheral to the container.

Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a single-wire bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the bus endpoints.

Abstract: A card-type storage device includes a processing chip and a memory module. The processing chip is selectively operated in a data accessing mode or a data uploading mode. The memory module is electrically connected with the processing chip. A first data set generated by the medical device at a first time point and a second data set generated by the medical device at a second time point are stored in the memory module. In the data accessing mode, a first storage list is established by the processing chip according to the first data set, and the first storage list is updated as a second storage list according to the second data set. If the processing chip judges that the second data set satisfies a predetermined condition, the processing chip enters the data uploading mode.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: Priority reversing data traffic for latency sensitive peripherals, including receiving a connection notification and parameters of a peripheral; identifying, from the parameters, that an interface type associated with the peripheral is a bulk interface, the bulk interface associated with a first communication channel between the IHS and the peripheral and having a first latency; determining, based on the bulk interface type and a data traffic priority associated with the peripheral, that the data traffic associated with the peripheral is priority-inversed; in response to a communication request by an application executing on the IHS for communication with the peripheral, determining that the data traffic associated with the peripheral is priority-inversed, and in response, placing the data traffic in a queue associated with a second communication channel defined between the IHS and the peripheral, the second communication channel having a second latency, wherein the first latency is greater than the second la

Abstract: A memory contains a linked list of records representative of a plurality of data transfers via a direct memory access control circuit. Each record is representative of parameters of an associated data transfer of the plurality of data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.

Abstract: A data transmission method and an apparatus used in a virtual switch technology are provided, and the method includes: receiving an IO request of a virtual machine VM for accessing a file or a disk, and When the IO request is to be sent to a physical NIC by using a user mode Open vSwitch (OVS), converting the IO request into an Internet Small Computer Systems Interface (iSCSI) command in a user mode, and then sending the iSCSI command to the user mode OVS, where the user mode OVS sends the iSCSI command to the physical NIC.

Abstract: An electronic device and method of operating the electronic device are provided. The electronic device includes a housing, a first connector configured to be exposed to outside of the housing and include a first number of pins, a second connector configured to be exposed to the outside of the housing and include a second number of pins, and a circuit configured to provide an electrical connection between the first number of pins and the second number of pins, wherein the first number is different from the second number, and wherein, when the first connector is connected with a first external electronic device and the second connector is connected with a second external electronic device, the circuit is configured to receive analog identification (ID) information through at least one pin among the first number of pins, and generate digital ID information at least partially based on the analog ID information so as to provide the digital ID information to at least one of the second number of pins.