Abstract: A process for forming a high quality polycrystalline semiconductor film on an insulating substrate which comprises using a MW-PCVD apparatus comprising a plasma generation chamber provided with a microwave introducing means and a film-forming chamber connected through a grid electrode to said plasma generation chamber, said film-forming chamber containing said insulating substrate positioned on a substrate holder made of a conductive material being installed therein, producing plasma by contacting a film-forming raw material gas with a microwave energy applied through said microwave introducing means in said plasma generation chamber and introducing said plasma into said film-forming chamber while applying a high frequency voltage with a frequency in the range of from 20 to 500 MHz between said grid electrode and said substrate holder to thereby cause the formation of said polycrystalline semiconductor film on said insulating substrate maintained at a desired temperature.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A semiconductor device is produced through processes that; ionized material is poured into a predetermined depth of a silicon substrate so as to be made into etching stopper layer, a predetermined area of the silicon substrate is etched up to the depth of the etching stopper layer so as to form a concave portion, a compound semiconductor chip is accommodated in the concave portion, insulating film is formed covering a space between the surrounding wall of the concave portion and the side wall of the compound semiconductor chip so as to be patterned, and that a second thin film circuit is so formed on the patterned insulating film as to connect between the electrodes on the compound semiconductor chip and a first thin film circuit which is previously formed on the surface of the silicon substrate.

Abstract: A method of manufacturing a semiconductor device comprises the steps of performimg selective vapor growth on a semiconductor substrate, and polishing a surface of an insulative film formed on said semiconductor substrate subsequent to the selective vapor growth step.

Abstract: A method of passivation of Hg.sub.1-x Cd.sub.x Te and similar semiconductors by surface oxidation (such as anodic) followed by chemical conversion of the oxide to either sulfide or selenide or a combination of both is disclosed. Preferred embodiments provide sulfide conversion by immersion of the oxide coated Hg.sub.1-x Cd.sub.x Te in a sodium sulfide solution in water with optional ethylene glycol and the selenidization by immersion in a solution of sodium selenide plus sodium hydroxide in water and ethylene glycol. Also, infrared detectors incorporating such sulfide and selenide passivated Hg.sub.1-x Cd.sub.x Te are disclosed.

Abstract: In a gaseous glow-discharge process for coating a substrate with semiconductor material, a variable electric field in the region of the substrate and the pressure of the gaseous material are controlled to produce a uniform coating having useful semiconducting properties. Electrodes having concave and cylindrical configurations are used to produce a spacially varying electric field. Twin electrodes are used to enable the use of an AC power supply and collect a substantial part of the coating on the substrate. Solid semiconductor material is evaporated and sputtered into the glow discharge to control the discharge and improve the coating. Schottky barrier and solar cell structures are fabricated from the semiconductor coating. Activated nitrogen species is used to increase the barrier height of Schottky barriers.

Abstract: A method of forming a shallow junction comprises the step of: forming a film including a hydrogen compound with one element selected from the group of boron, phosphorus arsenic to a thickness of several atom layers to 1000 .ANG. on a silicon substrate and annealing the film, whereby an impurity region having a depth of 1000 .ANG. or less and an impurity concentration of 10.sup.18 to 10.sup.21 cm.sup.-3 is formed in the surface layer of the silicon layer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A method for the low temperature fabrication of doped polycrystalline semiconductor alloy material. The method includes the steps of exposing a body of semiconductor alloy material to a reaction gas containing at least a source of the dopant element, and establishing an electrical potential sufficient to sputter etch the surface of said layer, while decomposing the reaction gas. This allows for the deposition of a layer of doped amorphous semiconductor alloy material upon the body of semiconductor alloy material. Thereafter, the doped layer of amorphous semiconductor alloy material is exposed to an annealing environment sufficient to at least partially crystallize said amorphous material, and activate the dopant element.

Abstract: A method of depositing a layer of doped or undoped wide band gap oxide material by chemical spray pyrolysis, upon a continuously advancing, elongated web of substrate material in a continuous, roll-to-roll process.

Abstract: This invention relates to a method for forming a boron-containing film of high quality on the surfaces of semiconductor wafers by CVD or epitaxial techniques using reaction gases including at least boron trifluoride.

Abstract: Hydrogen Plasma surface passivation of III-V Semiconductors is critically dependent on exposure time and pressure because of competition between plasma passivation and damage. Proper control of pressure according to the invention yields reproducible and stable passivation. Improved passivation is obtained using high pressure hydrogen plasmas, i.e. above 1 Torr.

Abstract: An improved process is described for depositing TiW/TiWN/TiW/Au metallization which provides superior adhesion properties, excellent barrier properties and which is suitable for use with metal line widths of the order of one micron or smaller. It is important in order to obtain these properties to ensure that the layer immediately underlying the gold layer by substantially pure TiW deposited in a nitrogen free sputtering atmosphere. To this end, the gas supply manifolds and deposition chamber are purged and the chamber evacuated following deposition of the TiW layer and prior to deposition of the TiWN layer underlying the gold layer. A final TiW layer is also conveniently placed on top of the gold layer to act as an etching mask.

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.

Abstract: A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dpoants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.

Abstract: A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas which is excited in a diode plasma reactor (100) which has an RF power source (13) applied to one of two parallel electrodes. The etching occurs in selected areas in a photoresist pattern (44) residing over the ZnS or HgCdTe layer (42). Wet etching the layer (42) with a wet etchant (54) following the dry etching, improves the via (50) by making the walls (48) smoother, and allowing for expansion of the vias (50) to a dimension necessary for proper operation of a HgCdTe-based infrared detector.

Abstract: A semiconductor device such as a solar cell, photodiode and solid state imaging device comprises a semiconductor layer made of amorphous silicon formed on a given substrate, and a transparent conductive layer formed by an interfacial reaction between the amorphous silicon and a metallic film directly formed on the amorphous silicon. This transparent conductive layer is used as a transparent electrode of the device and if necessary the remainder after having partially removed the metallic film for the transparent conductive layer is used as a conductive layer and light shielding film.

Abstract: In a method for forming a pattern, by selectively irradiating a charged particle beam onto a substrate in an atmosphere containing a raw material gas, a resist pattern comprising a material which is produced on the substrate from the raw material gas is formed, wherein a pressure of the raw material gas is set to 10.sup.-7 to 10.sup.-5 Torr, an accelerating voltage of the charged particle beam is set to 0.5 to 6 kV, and a beam current of the charged particle beam is set to 10.sup.-13 to 10.sup.-7 A. Thus, a resist pattern of an ultrafine width can be stably formed in a relatively short time.

Abstract: A dry etching method for refractory metal or its compound uses a mixed gas of an etchant gas for etching said refractory metal and a deposit gas for depositing said refractory metal. Halide of the etched refractory metal is used as the deposit gas. By using such a mixed gas, the refractory metal is etched at a portion where ion assist is strong, while the refractory metal is deposited at a portion where the ion assist is weak. In the dry etching, the ion mostly hits the surface of the object facing against the anode and hence the ion assist is strong, while the ion assist is weak at the side wall. Accordingly, the refractory metal is etched at the bottom surface of an etched groove, but at the side wall of the groove the refractory metal is deposited. This deposited metal protects the side wall from side etching. Therefore a fine pattern having a high aspect ratio etching is achieved.

Abstract: In a process for deposition of material onto a substrate, for example, the deposition of metals or dielectrics onto a semiconductor laser, the material is deposited by providing a colloidal suspension of the material and directly writing the suspension onto the substrate surface by ink jet printing techniques. This procedure minimizes the handling requirements of the substrate during the deposition process and also minimizes the exchange of energy between the material to be deposited and the substrate at the interface. The deposited material is then resolved into a desired pattern, preferably by subjecting the deposit to a laser annealing step. The laser annealing step provides high resolution of the resultant pattern while minimizing the overall thermal load of the substrate and permitting precise control of interface chemistry and interdiffusion between the substrate and the deposit.