Abstract: An apparatus and a method for the etching of semiconductor materials is disclosed. The apparatus includes a process chamber which includes a plasma generator remote from and in fluid communication with the process chamber. The remote plasma generator includes an inlet tube, a discharge tube in fluid communication with the inlet tube, an excitation cavity surrounding the discharge tube, an outlet tube in fluid communication with the discharge tube and a process chamber, and an injection tube in the outlet tube.

Abstract: A method is described for the formation of high purity thin films on a semiconductor substrate. In the preferred embodiment of the invention a thin film is formed on a semiconductor substrate in a plasma enhanced chemical vapor deposition system. Energized silicon ions are obtained by mass analysis and are accelerated into a hydrogen-free plasma. A reaction occurs between energized atoms within the plasma and the energized silicon ions resulting in the deposition of a thin film on the semiconductor substrate.

Abstract: A method for rapidly thermal processing a semiconductor wafer (1) by irradiation with electromagnetic radiation which provides that the majority portion of the energy required for heating the semiconductor wafer (1) is transmitted with at least single-sided irradiation of the semiconductor wafter (1) with electromagnetic radiation from a main irradiation arrangement (62) and the intensities (I.sub.M, I.sub.R) of the radiation directed onto the central region (6) and of the radiation directed onto the edge regions (5) are identical. The temperatures in the central region (6) and in the edge regions (5) of the semiconductor wafer (1) are maintained identical during the entire tempering process in order to increase the yield, and an additional electromagnetic radiation is directed onto the edge region (5) of the semiconductor wafer for compensating for the radiation of heat occurring faster at the edge region (5) of the semiconductor wafer (1).

Abstract: A metal for fabricating contact structures through via openings in VLSI circuits employs a dual layer of refractory metal. A thin titanium layer is deposited, over which a molybdenum layer is formed. An annealing treatment further improves contact resistance characteristics. The method results in a contact structure which exhibits desirable properties of thermal compatibility, step coverage, contact resistance and improved processing characteristics.

Abstract: The present invention is directed towards the production of a single crystal semiconductor device mounted in intimate contact with a polycrystalline CVD diamond substrate which allows the high heat conductivity of diamond to keep the device cool. This device is made by a method comprising the steps of placing in a reaction chamber, a single crystal of silicon heated to an elevated CVD diamond-forming temperature. A hydrocarbon/hydrogen gaseous mixture is provided within the chamber and is at least partially decomposed to form a polycrystalline CVD diamond layer on said silicon. During the deposition/growth phase, an intermediate layer of single crystal SiC has been found to form between the single crystal of silicon and the polycrystalline CVD diamond layer. In the next step of the process, the silicon is etched or removed to reveal the single crystal SiC supported by the polycrystalline CVD diamond layer. Finally, a semiconductor layer (e.g.

Abstract: A novel fabrication method is disclosed for fabricating a bipolar transistor having a digitated emitter electrode and a contiguous polysilicon region acting as a self-aligned base contact. The process substantially reduces the parasitic capacitances as well as eliminates the need for the intrinsic base region to be exposed to multiple etching, which results in the fabrication of small and reproducible base widths.A first polysilicon layer is deposited over the surface of a semiconductor substrate and, then, implanted with base dopants, which are driven into the surface of the active region by a furnace process for forming an intrinsic base region. Emitter dopants are next implanted into the first polysilicon layer. Subsequently, a nitride layer is deposited and the digitated emitter fingers patterned by selective etching.

Abstract: Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle < about 90.degree., is transferred by RIE, using CF.sub.4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount.

Abstract: A method is provided for forming a contact plug (40) in a contact (34) on a semiconductor substrate (30). A dielectric layer (32) is applied to the substrate (30) and then etched to form the contact (34). A layer (38) is then formed over the dielectric (32) and the contact (34). The layer (38) is removed from all surfaces, except the vertical sidewalls (36) within the contact (34). A metal plug (40) is then deposited in the contact (34) forming cup-shaped layers (42). The nonselectivity of the layer (38) allows the metal of plug (40) to be applied to the contact (34) without encroaching upon the substrate (30) or forming bumps on the surface (44) of the dielectric (32).

Abstract: A process is disclosed for the treatment of the backside or back surface of a semiconductor wafer such as a silicon wafer. By spacing the back side of a semiconductor wafer a predetermined distance from a cathode in a vacuum chamber and controlling the rf power and the pressure, a confined plasma may be used both to clean the back side of the wafer to remove impurities, including moisture and other occluded gases; as well as to deposit a layer of oxide on the back surface of the wafer to inhibit subsequent deposition of poorly adherent materials on the back side of the wafer which might otherwise flake off during processing of the front side of the wafer to form integrated circuits thereon.

Abstract: A method of heat treatment for purifying a Groups II-VI compound semiconductor and for producing a purity Groups II-VI compound semiconductor crystal using a sealed container placed a Groups II-VI compound semiconductor crystal as a raw material is disclosed. The process includes heating means applied to the sealed container having a temperature difference which has a high-temperature zone and a low-temperature zone into the sealed container, placing the raw material into the high-temperature zone of the sealed container, using a heat atom making an atmosphere of either a Group II element or a Group VI element, or a mixed atmosphere of either which is necessary to treat the Groups II-VI compound semiconductor into the sealed container, and using a Groups II-VI compound semiconductor as raw material.

Abstract: A Bi-CMOS device comprises a first insulating layer formed on a principal surface of a semiconductor substrate to extend outwardly from an edge portion of a base region of a bipolar transistor and from an edge portion of each source/drain region of each MOS transistor. A first polycrystalline semiconductor layer is formed on and in contact with a surface area of the base region of the bipolar transistor and a surface area of each source/drain region of each MOS transistor so as to extend on the first insulating layer. A second insulating layer is formed to cover the first polycrystalline semiconductor layer, a base-emitter junction exposed at the principal surface of the substrate and a portion of each of the base region and the emitter region adjacent to the exposed base-emitter junction. The second insulating layer also covers an inside edge of each source/drain region of the MOS transistors, and portions of each source/drain region and a channel region adjacent to the inside edge.

Abstract: This invention provides a method for fabricating a semiconductor device comprising the steps of forming buried layers on the silicon substrate; etching an epitaxial layer after said layer is grown up, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed remained the same thickness as grown up; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor. High efficiency and high integration is easily attained in fabricating the high speed bipolar transistor and high performance CMOS transistor on same chip and by reducing the difficulty in processing according to the method of present invention.

Abstract: An improved masking stack (63) comprises a pad oxide (58), polysilicon (60) and nitride (62). After forming a photoresist pattern (64) over the stack (63), an anisotropic etch is performed to remove the nitride (62) and a portion of the polysilicon (60) not covered by the pattern (64). Another etch is performed to remove the remaining polysilicon (60) to leave at least a portion of the pad oxide (58). A boron implant (66) is conducted to form implant areas (68 and 70) within the unmasked silicon active device layer (56). A portion of the implant areas (68 and 70) is masked with nitride (72), and the unmasked silicon layer (56) is then etched. The masking stack (63) and the nitride (72) is removed and unprotected silicon layer (56) and implant areas (68 and 70) are covered with an oxide forming the silicon dioxide mesa (78).

Abstract: A Schottky-type diode is fabricated by a process that enables the diodes conductor-to-semiconductor barrier height .phi..sub.B to be controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). In fabricating one version of the diode, a metallic layer (70) consisting of two or more metals such as platinum and nickel is deposited on an N-type silicon semiconductor (68) and heated to create a metal silicide layer (72) consisting of a lower layer (62) and an upper layer (74) of different average composition. A portion of the upper layer is then removed, allowing .phi..sub.B to be adjusted suitably.

Abstract: A method for selectively etching higher aluminum concentration AlGaAs in the presence of lower aluminum concentration AlGaAs or GaAs, preferably at room temperature. The AlGaAs is first cleaned with a solution of NH.sub.4 OH and rinsed. The AlGaAs is then etched in a solution of HF. If photoresist is used on the AlGaAs, the photoresist may first be baked to increase the adhesion of the photoresist to the AlGaAs and to "toughen" the photoresist to reduce undercutting thereof. Agitation is applied to the AlGaAs or the etchant to assist in the uniform etching of the AlGaAs.

Abstract: The invention relates to a method of manufacturing a semiconductor device, in which methylated silyloxy groups are formed on a silicon oxide layer which protects a PN junction, the methylated silyloxy groups being formed to reduce the leakage current of the device.The method employs a solution in which an amine is present which is at least di-substituted.

Abstract: The present invention is a contact etch method which simultaneously smoothes a reflowed oxide profile so that separate phanarization photoresist coat and etch steps are unnecessary. This method is characterized in that it is fast, uses only one photoresist mask layer, etches contacts to poly and to substrate simultaneously, is done entirely with plasma etch technology in a single reactor, and builds up less polymer in the plasma reactor. The novel method eliminates a coat and an etch step, improving yield and reducing fabrication time. Lower polymer buildup means higher yields due to a cleaner process, and less downtime for reactor chamber cleaning.

Abstract: A method for preventing cross-contamination of semiconductor wafers during processing comprising covering a surface portion of a support assembly with a process compatible material, engaging a semiconductor wafer with the support assembly, processing the wafer while it is engaged with the support member, and removing the process compatible material from the support assembly after said material is considered to be contaminated. A shield particularly adapted for this process includes a shield portion made from a process compatible material and a process-compatible adhesive for attaching the shield portion to the support assembly.

Abstract: The dopant body of arsenic for doping of a semiconductor substrate, e.g., silicon wafer, is a sintered body of a powder mixture comprising silicon arsenide, silica and, optionally, arsenic oxide in a specified proportion. The dopant body can be easily prepared and has various advantages over conventional elementary arsenic powder or a shaped body of silicon arsenide alone in respect of the high mechanical strength of the dopant body and absence of the problem of environmental contamination.

Abstract: Disclosed herein is a process for forming a silicon-containing semiconductor thin film, said process comprising the steps of causing a film-forming raw material gas containing silicon atoms as the conventional atoms in the molecule to be adsorbed in liquid form on the cooled substrate surface and subsequently causing the liquefied film-forming raw material gas to react with chemically active hydrogen atoms, thereby solidifying the silicon-containing material and forming a thin film on the substrate surface.The process of the present invention provides good step coverage and smoothens the substrate surface. It also makes it possible to increase the degree of integration of memory devices, photosensitive devices, image inputting devices, imaging devices, etc. Moreover, it makes it possible to realize the three-dimensional integrated circuits.