Abstract: A semiconductor integrated circuit device having a read-only memory which comprises a plurality of first gate electrodes arranged on a semiconductor substrate in a first direction maintaining a predetermined distance, a plurality of second gate electrodes that are arranged among said first gate electrodes and are partly overlapped on said first gate electrodes, and regions of data-writing impurities positioned under the first and second gate electrodes. The impurities for writing data are introduced through the first or second gate electrodes using the overlappings of the first and second gate electrodes as masks.

Abstract: The invention provides a method for making a new semiconductor base material comprising thin layers of amorphous, hydrogenous carbon (a-c:H) with a specific electrical resistance of between 10.sup.1 and 10.sup.8 .OMEGA..cm and a charge carrier concentration (n+p) of between 10.sup.10 and 10.sup.18 cm.sup.-3, respectively at room temperature. The new semiconductor base material can be manufactured in thin layer technology with the application of band processes and exhibits a charge carrier mobility of at least 1 cm.sup.2.v.sup.-1.s.sup.-1.

Abstract: An improved process for the selective deposition of tungsten on a masked semiconductor wafer is disclosed which comprises cleaning the surfaces of the wafer in an air-tight cleaning chamber, then transferring the cleaned wafer to a vacuum deposition chamber such as a CVD chamber for selective deposition of tungsten thereon without exposing the cleaned wafer to conditions which would recontaminate the cleaned wafer prior to said deposition, and then selectively depositing tungsten on the unmasked surfaces of the cleaned wafer.

Abstract: The invention provides electroactive passivation layers for semiconductor components comprising a thin layer of amorphous, hydrogenated carbon.

Abstract: A semiconductor substrate having first and second opposing surfaces is provided with a plurality of semiconductor elements having their electrodes arranged on the first surface. A plurality of small recesses are first formed in the second surface at locations opposite selected ones of the electrodes of the semiconductor elements. After the formation of the small recesses, the material of the substrate in and around the small recesses is etched away so that a larger recess encompassing the small recesses is formed and, at the same time, the small recesses are caused to extend through the substrate to thereby form through-holes which extend from the larger recess to the selected ones of the electrodes.

Abstract: A method of fabricating high density multi-chip interconnects whereby one or more polymer layers thereon are cured at approximately room temperature utilizing high energy electron bombardment. The polymer layers, typically in the range of five to twenty microns in thickness, cured in accordance with the present invention, have very low ambiant temperature interlayer stresses, resulting in higher reliability and/or a wider operating temperature range for the finished high density multi-chip interconnect. In addition, curing times are grossly reduced, thereby making the manufacturing processing much more orderly and rapid. Interlayer adhesion of polymer layers cured in accordance with the present invention may be enhanced by the baking of the same at an elevated temperature below the glass transition temperture for the polymer. Various methods and parameters are disclosed.

Abstract: A semiconductor device is disclosed in which a deposited non-oxide layer (44) overlies and physically contacts another non-oxide layer (38) so that no intervening oxide layer is present. The device is fabricated by performing an insitu etch and deposition process. In one embodiment, the device (36) is sealed in a LPCVD chamber (10) and etched using gaseous anhydrous hydrofluoric acid to remove an oxide (40) from one non-oxide layer (38). Then, without exposing the device to a water rinse or to the atmosphere, a chemical vapor deposition process applies the deposited layer (44) upon the other layer (38).

Abstract: A method for reducing the line widths produced by patterning a semiconduc substrate with a multilayer resist mask employs a `spacer`-forming oxide layer which is non-selectively formed over the mask structure after an aperture for exposing a lower resist layer has been formed in an upper portion of the multilayer mask, but prior to etching a lower resist layer. The oxide layer is subjected to a dry systemic etch to vertically remove material of the oxide layer down to the surface of the lower resist layer. Because of the substantial step coverage of the oxide layer, a `spacer` or `stringer` portion remains along the sidewalls of the original aperture in the upper portion of the mask, whereby the dimensions of the exposure window are reduced. Retaining this sidewall spacer as an integral part of mask structure permits narrower line widths to be replicated in the underlying substrate.

Abstract: A single mask method for providing multiple masking patterns, using excess etching techniques, which is usable for developing a semiconductor substrate for a semiconductor device which results in an increased current being required before latchup occurs in the semiconductor device.

Abstract: Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.

Abstract: The process of this invention includes forming and patterning a first layer of photoresist to form first lines of photoresist having substantially minimum lithographic widths, forming first elements between the first lines of photoresist, removing the photoresist, forming a sidewall member on each side edge of the first elements, forming a second layer over the structure, and etching to electrically insulate the first elements and the second elements at the sidewalls. Alternatively, the structure is coated with another layer of photoresist after formation of sidewall member on each side of the first elements. The layer of photoresist is patterned to form second photoresist lines that cover alternating sidewall members. The exposed sidewall members are removed. Strips are formed between the second photoresist lines. After removal of the second photoresist lines, the structure is etched as before. However, in this embodiment, lateral extensions of the first elements are formed.

Abstract: A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas which is excited in a diode plasma reactor (100) which has an RF power source (13) applied to one of two parallel electrodes. The etching occurs in selected areas in a photoresist pattern (44) residing over the ZnS or HgCdTe layer (42). Wet etching the layer (42) with a wet etchant (54) following the dry etching, improves the via (50) by making the walls (48) smoother, and allowing for expansion of the vias (50) to a dimension necessary for proper operation of a HgCdTe-based infrared detector.

Abstract: A semiconductor device has a device section and a peripheral section outside the device section. A main vernier pattern is formed in the peripheral section for inspecting finely an alignment state in a first direction, and a subsidiary vernier pattern is formed in the peripheral section near the main vernier pattern for inspecting coarsely an alignment state in a second direction at a right angle to the first direction.

Abstract: This invention is directed to the fabrication of semiconductor devices, especially those comprising III-V and II-VI compound semiconductor materials, and involves Rapid Thermal Annealing (RTA) of semiconductor wafers, especially those implanted with a dopant(s). The invention is also concerned with a black-box implement used in combination with the RTA. The process includes enclosing a wafer to be annealed within a "black-box" comprising components of a black body material and subjecting the black box with the wafer therein to an RTA.

Abstract: A manufacturing method of a mask-ROM of two-layered gate electrode structure is provided. With this method, a cell transistor having a first-layered gate is converted into the depletion type according to data to be stored in the following manner. That is, a first conductive layer is insulatively formed over a semiconductor substrate of a first conductivity type, a silicon nitride film is formed on the first conductive layer, a polysilicon film is formed on the silicon nitride film, the polysilicon film is patterned and then altered into a silicon oxide film so as to increase its volume, and the silicon nitride film is patterned with the silicon oxide film used as a mask to form windows for permitting impurity to be doped therethrough. Then, impurity for converting cell transistors into the depletion type according to data to be stored is doped from the windows into the substrate through the first conductive layer.

Abstract: There is provided a semiconductor article together with a process for producing the same which article has a plurality of semiconductor single crystal regions comprising a semiconductor single crystal region of one electroconductive type and a semiconductor single crystal region of the opposite electroconductive type on the same insulator substrate. At least the semiconductor single crystal region of one electroconductive type being provided by forming a different material which is sufficiently greater in nucleation density than the material of the insulator substrate and sufficiently fine to the extent that only one single nucleus of the semiconductor material can grow and then permitting the semiconductor material to grow around the single nucleus formed as the center.

Abstract: In humid atmospheres (e.g., 40% relative humidity or above) solutions of 2,2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride/2,2-bis[4-(aminophenoxy)phenyl]hexafluoropropane polyimides tend to be unstable in the sense that during spin coating operations undesirable precipitate formation occurs on the rotating surface of the wafer. The result is the formation of unacceptable coatings due to their irregularity and lack of uniformity. Described are solutions of these polyimide polymers in a solvent containing one or more liquid aromatic hydrocarbons having a boiling point of at least about 110.degree. C. and one or more dipolar aprotic solvents having a boiling point of at least about 150.degree. C., such that the solution (a) contains on a weight basis from about 5% to about 50% of the polyimide, and (b) does not undergo precipitate formation during spin coating in an atmosphere of at least up to about 55% relative humidity.

Abstract: The disclosed photosensitive matrix comprises, in a standard way, a P type semiconductor substrate, an N type channel layer separated by narrow insulating zones into a plurality of columns and, on a thin layer of insulating oxide placed on the channel layer, a network of transfer grids extending perpendicularly to the insulating zones, dividing the columns into a large number of "pixels". According to the invention, the matrix has, between the substrate and the channel layer, a weakly doped P type base layer, in which are buried anti-blooming diodes consisting of a narrow, strong doped N type drain extending in a direction parallel to the insulation zones. Beneath the drain, there is a strongly doped, P type protective screen. The arrangement gives an optical aperture of the matrix close to unity and a spectral response that is improved towards the red side of the spectrum owing to the thickness of the base layer.

Abstract: In human atmospheres (e.g., 55% relative humidity or above) solutions of 2,2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride/2,2-bis[4-(aminophenoxy)phenyl]hexafluoropropane polyamic acid polymers tend to be unstable in the sense that during spin coating operations undesirable precipitate formation may occur on the rotating surface of a semiconductor wafer. The result is the formation of unacceptable coatings due to their irregularity and lack of uniformity. Described are solutions of these polyamic acid polymers in a solvent containing one or more cycloaliphatic ketones, such that the solution (a) contains on a weight basis from about 5% to about 40% of the polyamic acid and (b) does not undergo precipitate formation during spin coating in an atmosphere of up to at least about 55% relative humidity.

Abstract: A semiconductor device is made from a body of semiconductor material having a layer of dielectric material and a first layer of conductive material over a main face of the body, the layers each having an opening therein through which an area of the main face of the body of semiconductor material is exposed. A second layer of conductive material is formed over the sides of the opening and the conductor material, whereby the second layer of conductive material is in conductive contact with the first layer of conductive material along the sides of the opening. Material of the second layer of conductive material is removed to a depth such that a portion of the main face of the body of semiconductor material is exposed but a sidewall of conductive material remains along a side of the opening and provides an electrically conductive connection between the first layer of conductive material and the body of the semiconductor material.