Abstract: Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.

Abstract: A nitride semiconductor laser device comprises, on a principle face of a nitride semiconductor substrate: a nitride semiconductor layer having a first conductivity type; an active layer comprising indium, and a nitride semiconductor layer having a second conductivity type that is different from said first conductivity type, and on the surface of which is formed a stripe ridge; said principal face of said nitride semiconductor substrate having an off angle a (?a) with respect to a reference crystal plane, in at least a direction substantially parallel to said stripe ridge.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes forming a semiconductor layer of poly silicon, forming a gate insulating layer on the semiconductor layer, forming a conductive layer including a first metal layer and a second metal layer formed on the first metal layer, depositing and forming a photoresist pattern on the first and the second metal layer, forming a gate electrode by etching the conductive layer, wherein the gate electrode includes a double layered structure including the first metal layers having a narrower width than a width of the second metal layer, forming a source region and a drain region in the semiconductor layer by doping conductive impurities, ashing the photoresist pattern to expose a portion of the second metal, etching the exposed portion of the second metal layer, removing the photoresist pattern, and forming lightly doped drain regions having a lower concentration compared to the source region and the drain region by using the gate electro

Abstract: A multi-wavelength surface emitting laser for emitting light having different wavelengths includes a lower reflector, an active layer and an upper reflector which are integrally formed above one substrate. The multi-wavelength surface emitting laser is manufactured by forming a first surface emitting laser, partially removing a first upper reflector, a first active layer, and a first lower reflection layer by etching. A protection film is formed on the outer surface of the first surface emitting laser. A second surface emitting laser is formed by removing a second lower reflector, a second active layer, and a second upper reflection layer formed on the protection film by etching. The protection film is removed and first and second upper electrodes are formed on upper surfaces of the first and second upper reflection layers, respectively, and a lower electrode is formed on a bottom surface of the substrate.

Abstract: Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film component are described.

Abstract: A method of manufacturing a semiconductor device includes: forming a circuit element on a semiconductor substrate; forming a first insulation film on top to cover the circuit element; forming a first electrode on top; forming a ferroelectric film on the first electrode; forming a second electrode on the ferroelectric film; forming a mask film on the second electrode; etching the second electrode with the semiconductor substrate or a mounting electrode set to a first temperature using the mask film as a mask; etching the ferroelectric film with the semiconductor substrate or the mounting electrode set to a second temperature using the mask film as a mask, the second temperature being lower than the first temperature; and etching the first electrode with the semiconductor substrate or the mounting electrode set to a third temperature using the mask film as a mask, the third and first temperatures being approximately the same.

Abstract: A method for manufacturing a semiconductor device includes the steps of consecutively depositing a Poly-Si layer, a WN layer and a W layer on a SiO2 layer, forming a mask pattern on the W layer, selectively etching the W layer by using plasma in a first etching gas having a high etch selectivity ratio between W and WN, selectively etching the WN layer and the Poly-Si layer by using plasma in a second etching gas having a high etch selectivity between WN and Si, and selectively etching the Poly-Si layer 13 by using plasma in a third etching gas having a high etch selectivity between Si and silicon oxide.

Abstract: To provide an organic field effect transistor with stable characteristics and a long life span, an organic field effect transistor includes a gate electrode 8 formed on an organic semiconductor film 2 made of an organic semiconductor material with a gate insulating film 3 interposed therebetween; and a source electrode 6 and a drain electrode 7 provided so as to come in contacts with the organic semiconductor film with the gate electrode 8 interposed therebetween. At least one of the source electrode 6 and the drain electrode 7 is formed in contact with the organic semiconductor film 2 with charge injection layers 4 and 5 made of an inorganic material interposed therebetween.

Abstract: A method for manufacturing a semiconductor laser device is provided in which deformation of a cap layer and a third cladding layer is inhibited and a protruding portion of an intermediate layer is removed. By coating outer peripheral portions facing an intermediate layer of a third cladding layer and an etching stop layer with a resist, inevitably removing at least the third cladding layer, and etching the intermediate layer and a cap layer in a second etching step, a protruding portion of the intermediate layer is removed, and the cap layer is prevented from being etched undesirably, whereby a ridge portion without irregularities with respect to a direction substantially perpendicular to a lamination direction is produced, and increase of an operation voltage and decrease of external differential quantum efficiency are prevented.

Abstract: A magnetic memory cell for use in a magnetic random access memory array that uses the antiferromagnetic to ferromagnetic transition properties of FeRh to assist in the control of switching of the memory cell.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: A capacitor and a method for fabricating the same are provided. The capacitor includes: a substrate; an inter-layer insulation layer formed over the substrate and including a contact hole; a storage node formed over the inter-layer insulation layer and filled into the contact hole; a tantalum oxide layer of single crystal formed over the storage node; and a plate formed over the tantalum oxide layer.

Abstract: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask.

Abstract: An organic electronic device. The device includes a first electrode to inject or extract hole, the first electrode including a conductive layer and an n-type organic compound layer disposed on the conductive layer, a second electrode to inject or extract electron, a p-type organic compound layer disposed between the n-type organic compound layer and the second electrode. The p-type organic compound layer forms an NP junction between the n-type organic compound layer and the p-type organic compound layer. The energy difference between a lowest unoccupied molecular orbital (LUMO) energy of the n-type organic compound layer and a Fermi energy of the conductive layer is about 2 eV or less, and the energy difference between the LUMO energy of the n-type organic compound layer and a highest unoccupied molecular orbital (HOMO) energy of the p-type organic compound layer is about 1 eV or less.

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.

Abstract: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.

Abstract: A method of forming a multiple layer passivation film on a semiconductor device surface comprises placing a semiconductor device in a chemical vapor deposition reactor, introducing a nitrogen source into the reactor, introducing a carbon source into the reactor, depositing a layer of carbon nitrogen on the semiconductor device surface, introducing a silicon source into the reactor after the carbon source, and depositing a layer of silicon carbon nitrogen on the carbon nitrogen layer. A semiconductor device incorporating the multiple layer passivation film is also described.

Abstract: A heterosystem of two different materials, mismatched in terms of lattice constant or symmetry, may be formed with reduced defects by using a two step approach proposed in this invention. Nanowires are first grown on a semiconductor substrate, and then a thin film of the disparate crystallographically inconsistent material is grown from the nanowires through a two dimensional growth mode. The nanowire material may better match crystallographically to both the substrate and the grown film, or is simply the same as the grown film.