Abstract: Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.

Abstract: A Method of forming microelectromechanical optical display devices is provided. A sacrificial layer is formed above a substrate. A plurality of posts penetrating the sacrificial layer is formed. A reflective layer and a flexible layer are sequentially formed above the sacrificial layer and the posts. A photoresist layer is formed on part of the flexible layer. By performing wet etching using the photoresist layer as a mask, a portion of the flexible layer is removed to form a patterned flexible layer. The wet etching is stopped on the reflective layer. The photoresist layer is removed. By performing dry etching using the patterned flexible layer as a mask, a portion of the reflective layer is removed to form a patterned reflective layer. A mechanical layer is formed with the patterned flexible and reflective layers. The sacrificial layer is removed to release the mechanical layer.

Abstract: A swage hermetic sealing of a MEMS or microdevice or nanodevice package using high force. A cutting and flowing edge 430 is formed on a package cover which is pressed into a mating , integral gasket 425 on a package base. A material extension of the package cover 450 is simultaneously folded under the package base to supply force maintenance for permanent hermaticity. The swage hermetic sealing of single or an array of covers to an extended wafer or substrate is accomplished by a cutting and flowing edge 560. Permanent force maintenance is achieved through a re-entrant cavity 565 and annular ring 535 on the wafer or substrate.

Abstract: A MEMS system including a fixed electrode and a suspended moveable electrode that is controllable over a wide range of motion. In traditional systems where an fixed electrode is positioned under the moveable electrode, the range of motion is limited because the support structure supporting the moveable electrode becomes unstable when the moveable electrode moves too close to the fixed electrode. By repositioning the fixed electrode from being directly underneath the moving electrode, a much wider range of controllable motion is achievable. Wide ranges of controllable motion are particularly important in optical switching applications.

Abstract: A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.

Abstract: Substituted anthracene compounds and electronic devices containing the substituted anthracene compounds are provided.

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract: An organic light emitting device having a cathode, an anode and an organic layer structure disposed between the cathode and the anode, the organic layer structure comprising a hole injection layer doped with a p-type dopant, a hole transport layer, an emissive layer and an electron transport layer doped with an n-type dopant, wherein all of the layers in the organic layer structure are substantially made from the same organic host material. In particular, the organic host material is a bipolar organic material such as a derivative of fused aromatic rings. The emissive layer can be doped with a fluorescent dye or a phosphorescent dye.

Abstract: Lenses and certain fabrication techniques are described. A wide-emitting lens refracts light emitted by an LED die to cause a peak intensity to occur within 50-80 degrees off the center axis and an intensity along the center axis to be between 5% and 33% of the peak intensity. The lens is particularly useful in a LCD backlighting application. In one embodiment, the lens is affixed to the backplane on which the LED die is mounted and surrounds the LED die. The lens has a hollow portion that forms an air gap between the LED die and the lens, where the light is bent towards the sides both at the air gap interface and the outer lens surface interface. The lens may be a secondary lens surrounding an interior lens molded directly over the LED die.

Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

Abstract: In a manufacturing method for a semiconductor device, a main body wafer having an interlayer insulating film is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer through BPSG densification during formation of the interlayer insulating film. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).

Abstract: A test device for detecting current leakage between deep trench capacitors in DRAM devices. The test device is disposed in a scribe line region of a wafer. In the test device, a first trench capacitor pair has a first deep trench capacitor and a second deep trench capacitor connected in parallel. A first transistor has a first terminal electrically coupled to the first deep trench capacitor and a control terminal electrically coupled to a first word line. A second transistor has a first terminal electrically coupled to the second deep trench capacitor and a control terminal electrically coupled to a second word line. First and second bit lines are electrically coupled to the first and second transistors respectively. The first and second bit lines are separated and the first and second word lines are perpendicular to the bit line regions.

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

Abstract: A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially uniform, and the saturation time is comparatively long and ease to stably use, compared with a time at which repeatability of an apparatus control can be secured. The invention has been finalized focusing on the result. That is, if plasma irradiation starts, a dose is initially increased, but a time at which the dose is made substantially uniform without depending on a time variation is continued. In addition, if the time is further increased, the dose is decreased. The dose can be accurately controlled through a process window of the time at which the dose is made substantially uniform without depending on the time variation.

Abstract: A method of forming a gate insulating layer and nitrogen density measuring method thereof, by which a transistor having enhanced electric characteristics can be fabricated without employing separate ion implantation in a manner of providing parameters for enhancing perfection of the transistor via nitridation measurement. The method includes forming a first oxide layer on a silicon substrate having first to fourth regions defined thereon, patterning the first oxide layer in the first and fourth regions to have a predetermined thickness, and forming a nitride layer on the oxide layer in the third and fourth regions.

Abstract: A method of manufacturing an organic EL device that is capable of reducing the manufacturing cost by effectively using the material is provided. In the method of manufacturing the organic EL device including a white-light-emitting layer and a color filter, the white-light-emitting layer is formed by using a liquid droplet ejection method. Further, the color filters are also formed by using the liquid droplet ejection method. As a result, it is possible to reduce waste of the material and the manufacturing time.

Abstract: A ferroelectric capacitor circuit for sensing hydrogen gas having a closed integrated circuit package, a ferroelectric capacitor within the closed integrated circuit package, the ferroelectric capacitor having a bismuth oxide based ferroelectric layer being able to absorb hydrogen gas that is within the closed integrated circuit package, absorbed hydrogen gas chemically reducing a portion of the bismuth oxide based ferroelectric layer into bismuth metal, the ferroelectric capacitor having a ferroelectric voltage, the ferroelectric voltage having a voltage strength, and means for measuring a decrease in the voltage strength of the ferroelectric voltage of the ferroelectric capacitor.

Abstract: Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap.