Abstract: A light emitting device including a transistor structure formed on a semiconductor substrate. The transistor structure having a source region, a drain region, a channel region between the source and drain regions, and a gate oxide on the channel region. The light emitting device including a plurality of nanocrystals embedded in the gate oxide, and a gate contact made of semitransparent or transparent material formed on the gate oxide. The nanocrystals are adapted to be first charged with first type charge carriers, and then provided second type charge carriers, such that the first and second type charge carriers form excitons used to emit light.

Abstract: A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.

Abstract: An improved method of interconnecting electronic devices is described. In the method a blended material for forming a conducting layer and an insulating layer are deposited between a contact of a first electronic device and a second electronic device. The blended material leads to formation of a conductor overlayed by an insulator such that after formation, the conductor is capable of carrying current from the first electronic device to the second electronic device and the insulator forms a protective layer over the conductor.

Abstract: Described is a process to pattern adhesion and top contact layers in such a way that at least some portion of the top contact layers overlaps the adhesion layer, while another portion of the top contact layer overlaps with the bottom contacts, but does not overlap with the adhesion layer. The overlap between the top contact layer and the adhesion layer helps to hold the top contact layer onto the sacrificial layer. Because there is no overlap between the adhesion layer and the bottom contact, the removal of adhesion layer is no longer necessary, leading to better contacts and simplifying the fabrication process.

Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements.

Abstract: An electronic circuit device includes at least a first substrate and a second substrate, a spacer substrate interposed between the first substrate and the second substrate, an electronic component interposed between the first substrate and the second substrate, and at least one through-hole formed on the second circuit substrate opposing the first circuit substrate. The spacer substrate mutually connects the first substrate and the second substrate. The electronic component is connected to the first circuit substrate with the active surface of the electronic component. The through-hole penetrates from a first surface of the second circuit substrate opposing the first substrate to a second surface of the second circuit substrate. The first circuit substrate is connected to the electronic component.

Abstract: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.

Abstract: A semiconductor material (5) is grown in the windows (4) of a patterned mask layer (3) on a substrate (1). The semiconductor material (5) grows together over the mask layer (3) with semiconductor material (5) from adjacent windows to form a largely planar surface (7), which is suitable for the further growth of a component layer sequence (9). Through the choice of a substrate (1) having a smaller thermal expansion coefficient than the semiconductor material (5), particularly strong tensile stresses occur in the semiconductor material (5) or the component layer sequence (9) during cooling, which stresses lead to cracking. Since the semiconductor material (5) that has grown together forms a so-called coalescence region (6), having a high density of imperfections in the crystal lattice, these thermally governed cracks (13) are more likely to occur in this region.

Abstract: A semiconductor light emitting element includes an conductive oxide film containing at least one element selected from the group consisting of zinc, indium, tin, and magnesium that is electrically connected to the semiconductor layer. The conductive oxide film includes a plurality of voids in the vicinity of the interface with the semiconductor layer.

Abstract: Provided is a field effect transistor having an organic semiconductor layer, in which the organic semiconductor layer contains at least a tetrabenzo copper porphyrin crystal and has peaks at two or more of Bragg angles (2?) in CuK? X-ray diffraction of 8.4°±0.2°, 10.2°±0.2°, 11.8°±0.2°, and 16.9°±0.2°, and the tetrabenzo copper porphyrin crystal comprises a compound represented by the following general formula (1): (Wherein R2's each represent a hydrogen atom, a halogen atom, a hydroxyl group, or an alkyl group, oxyalkyl group, thioalkyl group, or alkylester group having 1 to 12 carbon atoms, and R3's each represent a hydrogen atom or an aryl group.

Abstract: A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

Abstract: A device for detecting radiation, typically in the infrared. Photons are absorbed in an active region of a semiconductor device such that the absorption induces an interband electronic transition and generates photo-excited charge carriers. The charge carriers are coupled into a carrier transport region having multiple quantum wells and characterized by intersubband relaxation that provides rapid charge carrier collection. The photo-excited carriers are collected from the carrier transport region at a conducting contact region. Another carrier transport region characterized by interband tunneling for multiple stages draws charge carriers from another conducting contact and replenishes the charge carriers to the active region for photo-excitation. A photocurrent is generated between the conducting contacts through the active region of the device.

Abstract: A quantum supermemory is based on the cells of nanostructured material. The nanostructured material includes consists of clusters with tunnel-transparent coatings. The clusters have sizes at which resonant electron features are manifested. The size is determined by the circular radius of the electronic wave, according to the formula r0=/(me?2c)=7.2517 nm, where is the Plank contstant, me is the electron mass, ?=1/137,036 is the fine structure constant, c is the speed of light. The cluster size is set within the range r0=4r0, and the width of the tunnel-transparent gap is less than r0=7.2517 nm. The nanostructured material stores energy (charge) uniformly along its whole volume with the specific density of 1.66*103 J/cm3. Based on this material energy-independent rewritable memory is obtained with the writing density up to 28 Gbyte/cm2, the maximum working temperature being 878° C. and the maximum timing frequency being 175 Ghz.

Abstract: In a production method of a micromachine having a space between first and second electrodes, a first electrode is formed on a substrate, and then a stopper film is formed on its surface. Next, a second insulating film is formed as to cover the stopper film. The thickness of the second insulating film is larger than a total thickness of the first electrode and stopper film. Then, second insulating film is polished. By this polishing, the stopper film is exposed to the outside to the outside, and is planarized. After forming an opening in the stopper film, a sacrifice film is burred in the opening. Surfaces of the sacrifice film and second insulating film are planarized, and a second electrode is formed on the second insulating film as to cross the sacrifice film. A space is formed between the first and second electrodes by removing the sacrifice film.

Abstract: In order to form a p-region in an InP-based photodiode, zinc doping must be performed. Due to the current trend toward the implementation of larger-sized InP wafers, there is a need for a solid phase diffusion method in which a ZnO thin film is applied to an epitaxial wafer, the wafer is heated, such that zinc is diffused from the ZnO thin film into the InP epitaxial layers. A mask having an upper layer made of a-Si is used as a diffusion mask. Since a-Si does not dissolve in hydrofluoric acid, the a-Si remains without dissolving when the ZnO is removed with hydrofluoric acid. Since the a-Si film remains, the edge of the pn junction is not exposed. The pn junction does not become degraded because the edge of the pn junction is covered and protected by the diffusion mask at all times.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a first insulating layer and a semiconductor layer in sequence on the gate line; depositing a conductive layer on the semiconductor layer; photo-etching the conductive layer and the semiconductor layer; depositing a second insulating layer; photo-etching the second insulating layer to expose first and second portions of the conductive layer; forming a pixel electrode on the first portion of the conductive layer; removing the second portion of the conductive layer to expose a portion of the semiconductor layer; and forming a light blocking member on the exposed portion of the semiconductor layer, the light blocking member having an opening exposing the pixel electrode.

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract: A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate the isolation region (305) to create a threshold voltage compensation region (318). After the compensation region (318) is created, the hard mask layer (304, 308) is patterned (218) to create a patterned hard mask. The patterned hard mask is then used in forming (222) a trench (323) in the isolation region (305) near the compensation region (318), and the trench (323) is then filled (224) with a dielectric material (338).

Abstract: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below both ends of the floating gate; a ferroelectric substance interposed between the silicon substrate and the floating gate inside the tunnel oxide film; a diffusion barrier film enclosing the ferroelectric substance; a control gate formed on the substrate including the floating gate; a gate oxide film formed below the control gate; spacers formed on both lateral walls of the laminated floating gate and control gate including the tunnel oxide film and gate oxide film, respectively; and source/drain regions formed within the substrate surfaces on both sides of the control gate including the spacers, respectively.

Abstract: In a method of forming semiconductor device, a semiconductor fin is formed on a semiconductor-on-insulator substrate. A gate dielectric is formed over at least a portion of the semiconductor fin. A first gate electrode material is formed over the gate dielectric and a second gate electrode material is formed over the first gate electrode material. The second gate electrode material is planarized and then etched selectively with respect to first gate electrode material. The first gate electrode material can then be etched.