Abstract: The group III-V nitride series semiconductor substrate has good-product yield when the band-edge peak light-emission intensity ratio ?=N1/N2 is ?<1, where N1 is a band-edge peak light-emission intensity at an arbitrary photoluminescence measurement position on the front side of the substrate, and N2 is a band-edge peak light-emission intensity on the back side of the substrate corresponding to the photoluminescence measurement position.

Abstract: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 ? gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

Abstract: Disclosed is a method of producing an LnCuOX single-crystal thin film (wherein Ln is at least one selected from the group consisting of lanthanide elements and yttrium, and X is at least one selected from the group consisting of S, Se and Te), which comprises the steps of growing a base thin film on a single-crystal substrate, depositing an amorphous or polycrystalline LnCuOX thin film on the base thin film to form a laminated film, and then annealing the laminated film at a high temperature of 500° C. or more.

Abstract: A method of forming a micro-display includes forming a device that includes forming a partially reflecting layer on a first substrate and forming a plate overlying the partially reflecting layer, and adhering the device to a second substrate.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: An organic electroluminescent display device according to an embodiment includes a connection electrode on a first substrate; and a luminescent element on a second substrate opposite to the first substrate, the luminescent element being connected to the connection electrode, the luminescent element having a contact part at least partially surrounded by a separator, wherein a first electrode, a second electrode and an organic common layer between the first electrode and the second electrode are located in the contact part.

Abstract: An integrated optoelectronic silicon biosensor that can detect biomolecules by the change of the optical coupling between the integrated light source and the integrated detector that is caused by the binding of the appropriately labeled analytes onto the recognition molecules, that have been previously immobilized onto the integrated optical fiber that connects the optical source with the detector. The device contains the optoelectronic silicon chip and its biological activation. The optoelectronic chip is realized following integrated circuits fabrication methods so as the light source, the detector and the optical fiber, that optically couples the light source with the detector, to be monolithically integrated on the same silicon substrate. The biological activation of the chip is performed through physicochemical modification of the chip surface in order to permit immobilization of the recognition biomolecules onto the optical fiber surface.

Abstract: An apparatus including a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus also includes an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to the substrate. The MRAM stack may comprise a plurality of substantially planar, parallel layers each oriented at an acute angle relative to the substrate.

Abstract: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.

Abstract: A MEM device and method for fabricating a MEM device. A MEM device comprising a lever mechanism residing along a substrate is disclosed. A contact material is deposited on a first surface of the lever mechanism. In one arrangment, the first surface is disposed towards the substrate. A first contact region may be deposited on the substrate. The first contact region attracts the lever mechanism towards the substrate such that the contact material becomes operationally coupled to a second contact region. The MEM device may also comprise a first anchor portion and a second anchor portion. The first and second anchor portions may be integral to a top surface of the substrate. Aspects of the invention are also particularly useful in providing an encapsulated MEM switching device.

Abstract: A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows and other higher temperature processes.

Abstract: A new method to prevent cracking at the corners of a semiconductor die during dicing is described. Dummy metal structures are fabricated at the corners of the die to prevent cracking. The design for the dummy metal structures can be generated automatically by a computer program.

Abstract: A thin film transistor and a fabricating method of a thin film transistor for a liquid crystal display device includes forming a polycrystalline silicon film on a substrate, the polycrystalline silicon film having square shaped grains; forming an active layer by etching the polycrystalline silicon film; forming a gate electrode over the active layer, the gate electrode overlapping the active layer to form a channel region, the channel region being formed inside one of the grains; and forming source and drain electrodes connected to both sides of the active layer.

Abstract: A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device using metal organic chemical vapor deposition by supplying a cobalt precursor having a formula Co2(CO)6(R1—C?C—R2), where R1 is H or CH3, and R2 is hydrogen, t-butyl, phenyl, methyl, or ethyl, as a source gas. Then, a capping layer is formed on the cobalt layer. A first thermal treatment is then performed on the semiconductor device in an ultra high vacuum, for example, under a pressure of 10?9-10?3 torr, to react silicon with cobalt. Cobalt unreacted during the first thermal treatment and the capping layer are then removed and a second thermal treatment is performed on the semiconductor device to form the cobalt disilicide (CoSi2) layer.

Abstract: A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so is the second set of conductive layers. Each of the second set of conductive layers is inserted between two first conductive layers, and dielectric layers are interposed between two conductive layers to form a multilayer electrode capacitor.

Abstract: A molecular device is provided. The molecular device comprises a junction formed by a pair of crossed electrodes where a first electrode is crossed by a second electrode at a non-zero angle and at least one connector species including at least one switchable moiety and connecting the pair of crossed electrode in the junction. The junction has a functional dimension ranging in size from microns to nanometers. The molecular device further includes a buffer layer comprising nanocrystals interposed between the connector species and the second electrode.

Abstract: Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer of quantum dot material, and optionally, one or more layers of reflective Bragg reflectors. A mask is deposited over a top layer and reactive ion-beam etching applied to define a plurality of heterostructures. The release layer can be dissolved releasing the heterostructures from the wafer. Some exemplary applications of these methods include formation of fluorophore materials and high efficiency photon emitters, such as quantum dot VCSEL devices. Other applications include fabrication of other optoelectronic devices, such as photodetectors.

Abstract: A method for producing an LED package is provided, the LED package includes an LED die, which has a light-emitting surface, a non-light-emitting surface opposite to the light-emitting surface, a first electrode and a second electrode arranged on the non-light-emitting surface, a reverse-voltage protection member arranged on the non-light-emitting surface of the LED die, a conductive member electrically connecting the respective electrode of the LED die and the respective pole of the reverse-voltage protection member, and two outer conductive members electrically connecting the selected electrode or pole to an exterior circuit. Wherein the reverse-voltage protection member has a first pole that is the first polarity and a second pole that is the second polarity; the polarity of each pole of the reverse-voltage protection member is opposite to that of the electrode of the LED die.

Abstract: A method for manufacturing a quantum-dot element is disclosed. The method includes the following steps. First, a deposition chamber having at least one atomizer and a substrate-supporting base is provided. The atomizer is connected to a gas inlet and a sample inlet. Afterwards, a sample solution is prepared composed of a plurality of functionalized quantum dots dispersed in a solvent. Simultaneously, a substrate is placed on the substrate-supporting base in the deposition chamber. Finally, the sample solution and a gas are transferred into the atomizer through the sample inlet and the gas inlet respectively for generating quantum-dot droplets, which subsequently deposit on the substrate in the deposition chamber. The quantum-dot element manufactured by the present invention has a uniform distribution of quantum dots that have a small size and, therefore, the quality of the quantum-dot element can be substantially improved.

Abstract: A device includes a folded flex substrate. A memory die is connected to a first side of the folded flex substrate. A logic die is connected to a second side of the folded flex substrate. A trace routing pattern of source voltage signals is identical to a trace routing pattern of collector voltage signals.