Patents Examined by Belur V Keshavan
  • Patent number: 7005390
    Abstract: Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the plasma depletes a surface organic group, raising the dielectric constant of the material. In the worst case, the damaged dielectric is destroyed during the wet etch removal of the antireflective coating in the via-first copper dual-damascene integration scheme. This issue is addressed by exposing the dielectric to silane coupling agents at various stages of etching and cleaning. Chemical reactions with the silane coupling agent both replenish the dielectric surface organic group and passivate the dielectric surface relative to the surface of the antireflective coating.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. RamachandraRao, David H. Gracias
  • Patent number: 6972222
    Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: December 6, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shu-Ying Cho, Chien-Ming Chung, Yuan-Chang Huang
  • Patent number: 6964902
    Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: November 15, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Jane A. Yater, Gowrishankar L. Chindalore, Craig T. Swift, Steven G. H. Anderson, Ramachandran Muralidhar
  • Patent number: 6930382
    Abstract: A semiconductor device includes a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 16, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanako Sawada, Keiichi Sasaki
  • Patent number: 6908797
    Abstract: The present invention provides a manufacturing method of a semiconductor device, which is able to improve on-current and mobility of a polycrystal TFT without disturbing a high integration level, and also provide a semiconductor device obtained in accordance with the manufacturing method.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: June 21, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tamae Takano
  • Patent number: 6869825
    Abstract: A method and apparatus for making a multiply folded BGA package design with shortened communication paths and more electrical routing flexibility. A package apparatus includes a substrate and a first integrated circuit (IC), wherein the first IC is electrically connected to the first face of the substrate, and wherein a first segment and a second segment of the substrate are both folded around the first IC. A second IC is electrically connected to the second face of the substrate, such that the second IC is connected to the first and second folded segments of the substrate abode the first IC.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 22, 2005
    Assignee: Intel Corporation
    Inventor: Chia-Pin Chiu
  • Patent number: 6855632
    Abstract: A Cu thin film deposition equipment of a semiconductor device is disclosed for improving deposition speed of a Cu thin film and lowering its corresponding cost. This equipment includes a load lock carrying out the steps before and after wafer processes, an aligner carrying out alignment so that a wafer reaches a desired position, a de-gas chamber removing residue such as gas produced on a surface of a wafer, and a feeding chamber provided with a robot placing the wafer in/out of each chamber. A pre-cleaning chamber cleaning the inside and the outside of a pattern using plasma on a wafer fed by the feeding chamber, a barrier metal deposition chamber, an adhesion glue layer (AGL) flash Cu deposition chamber, a CECVD deposition chamber, and a plasma treatment chamber are also provided with the equipment.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: February 15, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Gvu Pyo, Si Bum Kim
  • Patent number: 6849873
    Abstract: In liquid crystal display device having a multi-layer conductive layer, such conductive layer is formed using a photoresist pattern having different thicknesses depending on the position. Upper layer of the gate pad is removed using an etch mask of the photoresist pattern of different thickness. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire. Finally passivation layer is formed and an indium tin oxide layer is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: February 1, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Huh, Jong-Soo Yoon, Dong-Gyu Kim
  • Patent number: 6849498
    Abstract: Disclosed herein is a method of manufacturing a semiconductor capacitor. In the semiconductor capacitor manufacturing method, an amorphous film composed of non-doped silicon is formed. The amorphous film is changed to a lower film having projections and depressions defined in the surface thereof by heat treatment. An amorphous film composed of impurity-doped silicon is formed over the surface of the lower film. Further, the amorphous film composed of the impurity-doped silicon is changed to an upper film having projections and depressions defined in the surface thereof by heat treatment with the projections and depressions provided over the surface of the lower film as a basis. The semiconductor capacitor is equipped with an electrode having the lower film and the upper film.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: February 1, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroki Kuroki
  • Patent number: 6838305
    Abstract: A method of fabricating a solid-state imaging device is provided, which enables the formation of an anti-reflection film by oxidizing a surface of a metallic light-shield film without adding additional steps, even though the metallic light-shield film is composed of not only refractory metal silicide but also metals, including tungsten and molybdenum. The method comprises the steps of forming a metallic light-shield film on a light receiving sensor and a transfer electrode formed on a surface layer of a wafer, forming an opening on the metallic light-shield film on the light receiving sensor by etching, forming an interlayer film, and shaping the interlayer film into a lens shape by heat treatment. An atmosphere of either one or both of oxygen gas and ozone gas is prepared in a chamber for forming the interlayer film, and a surface of the metallic light-shield-film is oxidized before the interlayer film is formed.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: January 4, 2005
    Assignee: Sony Corporation
    Inventors: Kazuaki Moriyama, Takeshi Matsuda
  • Patent number: 6838296
    Abstract: A test device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices. A quadrilateral active area is disposed in the scribe line region, with four equilaterals and four vertex angles. Parallel first and second deep trench capacitors are disposed in the quadrilateral active area. The first deep trench capacitor has a first surface aligned with a second surface of the second deep trench capacitor. The first and second vertex angles of the four vertex angles have a diagonal line essentially perpendicular to the first and second surfaces. The first and second vertex angles are a predetermined distance from the first surface and the second surface respectively.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: January 4, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tie-Jiang Wu, Chien-Chang Huang, Bo-Ching Jiang, Yu-Wei Ting
  • Patent number: 6821833
    Abstract: A method of forming CMOS semiconductor materials with PFET and NFET areas formed on a semiconductor substrate, covered respectively with a PFET and NFET gate dielectric layers composed of silicon oxide and different degrees of nitridation thereof. Provide a silicon substrate with a PFET area and an NFET area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric layer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer and the PFET gate dielectric layer can have the same thickness.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Anthony I-Chih Chou, Toshiharu Furukawa, Patrick R. Varekamp, Jeffrey W. Sleight, Akihisa Sekiguchi
  • Patent number: 6797611
    Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.
    Type: Grant
    Filed: August 3, 2003
    Date of Patent: September 28, 2004
    Assignee: Nanya Technology Corp.
    Inventors: Kuo-Chien Wu, Yinan Chen
  • Patent number: 6777261
    Abstract: A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren Farnworth, Larry Kinsman, Walter Moden
  • Patent number: 6762068
    Abstract: A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6762109
    Abstract: A method of manufacturing a semiconductor device and a method of forming a capacitor allow the formation of a high-performance capacitor without increasing the number of process steps. A silicide protection film (11c) is formed to cover a lower electrode (6) of a capacitor. The silicide protection film (11c) is formed during the process step of forming another silicide protection film (11a). An upper electrode (19) of the capacitor is formed of metal film and opposed to the lower electrode (6) with the silicide protection film (11c) sandwiched in between. A portion of the silicide protection film (11c) which is sandwiched between the upper electrode (19) and the lower electrode (6) serves as a capacitor dielectric film.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: July 13, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Naofumi Murata
  • Patent number: 6759332
    Abstract: A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: July 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Larry A. Nesbit
  • Patent number: 6759304
    Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: July 6, 2004
    Assignee: STMicroelectronics SA
    Inventors: Philippe Coronel, Marc Piazza, Fran├žois Leverd
  • Patent number: 6746945
    Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a via hole, thereafter, the etching rate decreases. Accordingly, even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: June 8, 2004
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Toshiyuki Orita
  • Patent number: 6737363
    Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a low dielectric constant insulating film having a siloxane bond as main skeleton on a semiconductor substrate, causing a surfactant to permeate the low dielectric constant insulating film, and conducting a predetermined step on the low dielectric constant insulating film permeated with the surfactant in a state adapted to be exposed to water.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: May 18, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Nobuhide Yamada, Nobuo Hayasaka, Nobuyuki Kurashima