Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: A process of plasma-enhanced chemical vapor deposition of silicon oxynitride from a gas mixture of nitrous oxide and a silicon-containing gas employs a dual-power source of plasma generation and sustenance, to produce optimum properties of the deposited layer, for the purposes of passivation of the semiconductor surface, minimization of trapped energetic electrons, and protection of the integrated circuit device from moisture and other potentially deleterious effects.

Abstract: An apparatus for fabricating a semiconductor device having cooling jackets for preventing a gas from being exuded in a reaction chamber, thereby minimizing the generation of contaminating particles. The apparatus includes a reaction chamber having four cooling jackets respectively mounted on a first side wall adjacent to a wafer transfer chamber, a second side wall opposite to the first side wall, an upper wall and a bottom wall. A gate valve is disposed between the reaction chamber and the wafer transfer chamber and has a fifth cooling jacket. While fabricating a polysilicon film using the above apparatus, a pressure of a cassette chamber is controlled to be less than about 0.05 mtorr. Alternatively, a pressure of a cooling chamber and the wafer transfer are both controlled to be less than about 1.0 &mgr;torr.

Abstract: A cell-quadropole cell structure is disclosed which extends the principle of sharing the bitline-stud between two different cells (arranged in a one-dimensional line, e.g. w-direction) further to the maximal possible degree of a sharing in a two-dimensional area (x- and y-direction) consequently forming a cross of four cells around one bitline-stud with each drain region and buried strap extended to the side and the trench attached forming a hook like structure.

Abstract: A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

Abstract: A process for semiconductor device fabrication in which a Czochralski silicon substrate is implanted with boron is disclosed. The boron is implanted using an energy of about 500 keV to about 3 MeV and a dose of about 3.times.10.sup.13 /cm.sup.2 to about 3.times.10.sup.14 /cm.sup.2. In order to reduce the threading dislocation density in the substrate to less than about 10.sup.3 /cm.sup.2 at a depth in the substrate of at least about 0.5 .mu.m, after the implant, the substrate is annealed in a two-step process. First the substrate is annealed at a temperature in the range of about 725.degree. C. to about 775.degree. C. followed by an anneal at a temperature of at least about 900.degree. C. The duration of the first step is selected to provide a dislocation density of less than about 10.sup.3 /cm.sup.2 at the desired depth in the substrate.

Abstract: A polymer stud grid array for microwave circuits is proposed which includes an injection-molded, three-dimensional substrate that is fabricated from an electrically insulating polymer. The substrate includes a plurality of polymer studs which are arranged over the underside of the substrate and which are integrally formed with the substrate during the injection-molding process. Signal connections are formed on the studs which include an end surface that is capable of being soldered. Potential connections are formed on at least one of the studs. The potential connection also includes an end surface that is capable of being soldered. Striplines are also constructed which connect the studs to the microwave circuit. Each stripline includes a first structured metal layer disposed on the underside of the substrate, a dielectric layer disposed on the first metal layer and a second structured metal layer disposed on top of the dielectric layer.

Abstract: A method of fabricating a semiconductor device is disclosed for connecting a bit line to a semiconductor substrate in a self-aligned fashion in non-contacting relation to a word line and precluding a crystal defect in the semiconductor substrate which might induce a leakage current. An isolation insulative film (2), gate oxide films (3), gate electrodes (4) (word lines), and insulative films (5) are formed on a semiconductor (e.g., Si) substrate (1) in sequential order, and sidewalls (6a to 6f) are formed while substrate protective oxide films (6g to 6i) are formed so that the semiconductor substrate (1) is not exposed. Source/drain regions (261 to 263) are formed, and an insulative film (7) made of Si.sub.3 N.sub.4, SiON and the like is deposited. Then, an interlayer insulative film (8) is formed over the top surface. The insulative film (7) has an etching rate lower than that of the interlayer insulative film (8).

Abstract: A method of forming a trench capacitor over a semiconductor substrate comprises the following steps. First, a nitride layer is formed on the substrate. Then, a first oxide layer is formed on the nitride layer. Next, the first oxide layer and the nitride layer are etched to expose a portion of the surface of the substrate. An etching back step is performed to etch the nitride layer to pull back the sidewalls of the nitride layer. Next, the second oxide layer is formed above the first oxide layer, the nitride layer and the substrate. An etching step is done to form the trench structure on the substrate by using the first oxide layer as a mask. Then, a wet etching step is performed to remove the first oxide layer and the second oxide layer. Next, a doping step is done to form the doped region in the trench structure. A dielectric layer is then formed above the doped region. A conducting layer is formed on the dielectric layer, wherein the conducting layer is coupled with a drain.