Abstract: An in-situ cap for an integrated circuit device such as a micromachined device and a method of making such a cap by fabricating an integrated circuit element on a substrate; forming a support layer over the integrated circuit element and forming a cap structure in the support layer covering the integrated circuit element.

Abstract: A method for the fine tuning of a passive electronic component having at least a carrier substrate and at least one electrically conducting layer containing a material having a conducting nitride, a conducting oxynitride, a semiconductor, or chromium, by means of a focused laser emission, which laser emission induces a heating effect which heating effect causes the material to be converted to a locally electrically non-conducting material.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: A DRAM includes a MOSFET and a stacked capacitor in each memory cell. The stacked capacitor includes a bottom electrode substantially of a cylindrical shape, a top electrode received in the cylindrical-shape bottom electrode, and a capacitor dielectric film for insulation therebetween. The cylindrical shape of the bottom electrode allows a larger deviation for alignment between the capacitor and the capacitor contact.

Abstract: A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate s formed during the BEOL process. The transistor may by a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

Abstract: A high density, non-bussed semiconductor package and a full body gold (FBG) method for manufacturing semiconductor packages are provided to improve electrical and mechanical connections with semiconductors and other electronic components and devices. The semiconductor package is fabricated by developing circuitry on the wire bond side of the semiconductor package prior to developing the ball attach side. The copper circuitry on the wire bond side is fully covered and protected from the environment. Solder masks are applied directly to the semiconductor substrate or copper layer to avoid contact with gold. The ball attach area is covered and protected by metallic layers, such as nickel and gold, or an organic solderable material to eliminate weak solder mask-gold connections.

Abstract: A method of forming conducting diffusion barriers by depositing an initial film and implanting ions to modify the film is provided. An initial film having good step coverage is deposited over a semiconductor substrate. The initial material need not have the desired properties for a conducting diffusion barrier, but preferably contains one or more elements to be used in forming a desired film with the appropriate properties. The initial material is deposited by CVD, PECVD or IMP deposition. Ions are preferably implanted using plasma immersion ion implantation (PIII), although other methods are also provided. The method of the present invention produces binary, ternary, quaternary and other more complex films, while providing adequate step coverage.

Abstract: The present invention provides a semiconductor light-emitting device including a Si substrate, a first clad layer, and an intermediate layer of n-AlInN between the substrate and the first clad layer. The intermediate layer is formed of AlxGayInzN, wherein x+y+z=1, 0≦y≦0.5, and 5/95≦z/x≦40/60. Thus on the Si substrate there can be provided a nitride-based, light emitting semiconductor device of high quality capable of electrical conduction from the Si substrate.

Abstract: A lead frame made from Ni, a Ni alloy, Cu, a Cu alloy, Fe or an Fe alloy, comprising an inner lead part with a surface treatment layer of Ag or a Ag-containing alloy and an outer lead part with a surface treatment layer of an alloy containing Ag and Sn, wherein the latter surface treatment layer has a brightness of not less than 0.6 and Sn has the body-centered tetragonal lattice with the crystal orientation indices of from 1.5 to 5 at the (220) plane, not more than 0.9 at the (211) plane and not less than 0.5 at the (200) plane. The surface treatment layer is plated with utilization of a plating solution which contains one or more selected from alkane sulfonic acid, alkanol sulfonic acid and sulfamine acid as the acid component, one or more of tin methane-sulfonate and SnO as a tin salt, and one or more slected from silver methane-sulfonate, Ag2O and AgO as a silver salt.

Abstract: Provided with a laser diode and its fabricating method including the steps of: sequentially forming a first conductivity type clad layer, an active layer, a second conductivity type first clad layer, an etch stop layer, a second conductivity type second clad layer, a second conductivity type InGaP layer, and a second conductivity type GaAs layer, on a first conductivity type substrate; forming an insulating layer on the second conductivity type GaAs layer and patterning it, exposing a defined region of the second conductivity type GaAs layer; performing a reactive ion etching using the patterned insulating layer as a mask, etching the second conductivity type GaAs layer, the second conductivity type InGaP layer, and the second conductivity type second clad layer to a specified depth and remaining part of the second conductivity type second clad layer; forming a photoresist on the whole surface including the insulating layer and patterning it, exposing the residual second conductivity type second clad layer; p

Abstract: The present invention relates to a method of forming a contact pedestal for an electrical connection between a stack capacitor and a node location of a substrate. The present invention is characterized by forming, just based on patterning a mask layer twice, a hole in the shape of a stud in the dielectric material deposited over the node location, to make a contact pedestal in the shape of a stud for an electrical connection between a node location of a FET in a substrate, and a stack capacitor spaced from the substrate by the dielectric material.

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Abstract: The present invention relates to a method of crystallizing a silicon film, a thin film transistor, and a fabricating method thereof using the same. More particularly, the present invention relates forming a crystalline silicon film by crystallizing a silicon film using laser energy, and a thin film transistor and a fabricating method thereof using the same. The present invention includes forming a buffer layer on a substrate and forming an amorphous silicon film on the buffer layer wherein the amorphous silicon film includes a first region and second regions connected to both ends of the first region. The buffer layer is etched to a degree by using the amorphous silicon as a mask, wherein a space is formed under the first region and a central part of the second region contacts a remaining portion of the buffer layer. The amorphous silicon film is then crystallized.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: This invention provides a method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM. The DRAM on a predetermined area of a semiconductor wafer comprises memory cells arranged in a matrix format. Each memory cell comprises an N-type MOS transistor which comprises gate electrode layer, two spacers on two opposite side walls of the gate electrode layer, two lightly doped layers on the surface of the substrate below the two spacers, and two heavily doped layers act as the source and drain. This method uses two ion implantation processes to implant boron ions first into a region below one of the two lightly doped layers in a specified direction to form a first pocket implantation region, and then into a region below the other lightly doped layer in the opposite direction to form a second pocket implantation region so as to complete the pocket implantation.

Abstract: A method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors (FETs) is achieved. After forming a field oxide to electrically isolate device areas on a silicon substrate, an ultra-thin silicon nitride-oxide insulating layer is formed in two process steps. In the first process step a silicon nitride layer is formed on the device areas on the substrate using a low-pressure rapid thermal process (LP-RTP) and a reactant gas of ammonia (NH3) while insuring that the RTP tool is free of oxygen. Then a second process step is carried out sequentially in the same LP-RTP at an elevated temperature and using an oxygen-rich ambient (dinitrogen oxide N2O) as a reoxidation gas. The non-self-limiting characteristic of the ultra-thin-silicon nitride layer results in the controllable diffusion of the dissociated oxygen (O) and nitrous oxide (NO) through the silicon nitride layer to form a thin good quality silicon oxide layer on and in the substrate surface.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a titanium nitride layer on the first capacitor electrode. A tantalum pentoxide dielectric layer is then formed on an upper surface of the titanium nitride layer. A step is then performed to convert the underlying titanium nitride layer into a titanium oxide layer. A second capacitor electrode is then formed on the tantalum pentoxide layer. The step of converting the titanium nitride layer into a titanium oxide layer is preferably performed by annealing the tantalum pentoxide layer in an oxygen ambient in a range between about 700° C. and 900° C. This oxygen ambient provides free oxygen to fill vacancies within the tantalum oxide layer and also provides free oxygen which diffuses into the underlying titanium nitride layer.

Abstract: The present invention discloses a small spherical solar cell SS (spherical semiconductor) and the manufacturing method for the same, comprising: a spherical core 1; a reflective film 2 formed on the surface of core 1; a semiconductor thin film layer (p type polycrystalline silicon thin film 4a, n+ diffusion layer 7) which is approximately spherical and is formed on the surface of reflective film 2; a n+p junction 8 which is formed on semiconductor thin film layer; passivation film 9; and a surface protective film 10 of titanium dioxide; a pair of electrodes 11a, 11b connected to both sides of n+p junction 8. Other than spherical solar cell SS, the following are also disclosed: a spherical crystal manufacturing device; 2 types of spherical solar cells; 2 types of spherical photocatalytic elements; a spherical light emitting element which emits visible blue light; 2 types of spherical semiconductor device materials.

Abstract: A method of forming a gate electrode with a titanium polycide structure capable of preventing abnormal oxidation of the gate electrode when performing gate re-oxidation process, is disclosed. In the present invention, after forming a gate electrode having a stacked structure of a polysilicon layer and a titanium silicide layer, thermal-treating is performed under nitrogen atmosphere to form a TiN layer on the side wall of the titanium silicide layer, considering as silicon content of the titanium silicide layer is high, abnormal oxidation decreases. At this time, a titanium silicide layer having deficient Ti is formed on the side wall of the titanium silicide layer adjacent to the TiN layer. Therefore, after removing the TiN layer, the side wall of the titanium silicide layer having excessive Si (or deficient Ti) is exposed. Thereafter, gate re-oxidation process is performed. At this time, abnormal oxidation of the titanium silicide layer is prevented by the titanium silicide layer having excessive silicon.