Abstract: Provided is a reliable nonvolatile memory with a lower power consumption. A ferromagnetic interconnection which is magnetized antiparallel or parallel to a magnetization direction of a ferromagnetic pinned layer in a giant magnetoresistive device or a tunnel magnetoresistive device constituting the magnetic memory cell, is connected to a ferromagnetic free layer with a non-magnetic layer being interposed in between, the ferromagnetic free layer serving as a recording layer. Thereby, the magnetization of the recording layer is switched by use of a spin transfer torque.

Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a metallic barrier layer in the opening and in physical contact with the dielectric layer, a conductive material filling the remaining part of the opening, and an interlayer between and adjoining the metallic barrier layer and the conductive material. The interlayer is preferably a metal compound layer.

Abstract: In the case of providing an LDD region for a TFT, it is necessary to form separately an insulating film to be a mask or to contrive the shape of a gate electrode layer in order to have the concentration difference in impurities injected in a semiconductor film; therefore, the number of patterning steps has increased as a matter of course and the step has become complicated. A semiconductor device according to one feature of the invention comprises a semiconductor layer including a channel region, a pair of impurity regions, and a pair of low-concentration impurity regions; and a gate electrode layer having a single layer structure or a laminated structure, of which film thickness is not even, which is formed to be in contact with the semiconductor layer by sandwiching a gate insulating film therebetween.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: Marking lines or patterns are formed among dummy patterns or on a reference plain of a semiconductor device requiring analysis to enable easy location of a point on the semiconductor device.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.

Abstract: In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first memory container of the number of memory containers is in contact with the collar material along a side of a second memory container. An opening exists between the collar material along a corner of the memory container and the collar material along a corner of a third memory container.

Abstract: A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.

Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.

Abstract: In one embodiment, a LED lamp includes a heat sink including rows of exposed fins on one surface and a conductive member opposite the fins and including two electrically connected side positive electrodes, one or more negative electrode spaced from and between the positive electrodes, and one or more conductive positioning strips each between the negative electrode and either positive electrode; a light array mounted on the conductive member and including rows of LEDs divided into electrically parallel connected groups with the LEDs of each group being electrically series connected together, each LED including positive and negative pins secured to one conductive positioning strip and electrically connected to either positive electrode and the negative electrode respectively, a positive conductor electrically connected to either positive electrode; and a negative conductor electrically connected to the negative electrode.

Abstract: A solid-state imaging device capable of reducing an eclipse (blocking) of an incident light at a circumferential portion of a light receiving portion and realizing a larger angle of view and high-speed driving. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is adopted. Two shunt wirings extending in a horizontal direction are formed on the first transfer electrodes connected in a horizontal direction and, for example, four-phase transfer pulses are supplied to first transfer electrodes and second transfer electrodes on transfer channels through low-resistance shunt wirings extending in the horizontal direction.

Abstract: Novel structures of the photodetector having broad spectral ranges detection capability are provided. The photodetector can offer high quantum efficiency >95% over wide spectral ranges, high frequency response >10 GHz (@3 dB). The photodiode array of N×N elements is also provided. The array can also offer wide spectral detection ranges ultraviolet to 2500 nm with high quantum efficiency >95% and high quantum efficiency of >10 GHz, cross-talk of <1%. In the array, each photodiode can be independently addressable and can be made either as top-illuminated or as bottom illuminated type detector. The photodiode and its array provided in this invention, could be used in multiple purpose applications such as telecommunication, imaging and sensing applications including surveillance, satellite tracking, advanced lidar systems, etc. The advantages of this photodetectors are that they are uncooled and performance will not be degraded under wide range of temperature variation.

Abstract: A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.

Abstract: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a). If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source (3a) and the (ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).

Abstract: A conductor substrate for mounting a semiconductor element, at least a portion thereof mounting the semiconductor element being sealed with an insulating resin, wherein an uppermost surface layer of the conductor substrate comprises copper or an alloy thereof, and the conductor substrate is partly or entirely covered with a layer of copper oxide containing a hydroxide formed upon the surface treatment of the conductor substrate and a process of producing the conductor substrate as well as a process for the production of a semiconductor device using the conductor substrate.

Abstract: A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conductive bond pad in the reference direction, wherein the patterned support/interface layer includes a hole and a trench, wherein the hole is directly above the electrically conductive bond pad, and wherein the trench is not filled by any electrically conductive material; and (d) an electrically conductive solder bump filling the hole and electrically coupled to the electrically conductive bond pad.

Abstract: Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.

Abstract: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.