Abstract: Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

Abstract: Transistor devices are provided configured to operate at frequencies above a typical first cutoff frequency. In one aspect, a method is provided for configuring a transistor device to operate above a first cutoff frequency. The method comprises selecting a desired operating frequency range and a desired output power for a transistor associated with the transistor device, analyzing the effects of phase velocity mismatch on the overall gain of a plurality of different sized transistors, and evaluating the primary and secondary gain regions of the plurality of different sized transistors. The method further comprises selecting a transistor sized to provide the desired output power at or close to the desired operating frequency range based on the analysis of the phase velocity mismatch and the evaluation of the primary and secondary gain regions.

Abstract: A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer on an inner sidewall of an opening exposing the plate electrode by a plasma entire surface anisotropic etching.

Abstract: The present invention relates to a semiconductor device which comprises a plug layer which is embedded in a window penetrating an inter-layer insulation film, and flattened by using a chemical mechanical polishing, a titanium Ti film which is deposited to extend from the inter-layer insulation film to the plug layer, a titanium nitride TiN film which is deposited on the Ti film, a wiring layer which contains aluminum Al or copper Cu deposited on the TiN film, and an underlying film which is formed between the inter-layer insulation layer and the Ti film.

Abstract: A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region.

Abstract: Differentially strained active regions for forming strained channel semiconductor devices and a method of forming the same, the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; forming a doped area of the insulator region underlying a subsequently formed NMOS active region; patterning the upper semiconductor region to form the NMOS active region and a PMOS active region; carrying out a thermal oxidation process to produce a differential-volume expansion in the PMOS active region with respect to the NMOS active region; forming recessed areas comprising the insulator region adjacent either side of the PMOS active region; and, removing layers overlying the upper semiconductor region to produce differentially strained regions comprising the PMOS and NMOS active regions.

Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

Abstract: A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

Abstract: An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for the plural fuse elements.

Abstract: An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.

Abstract: A detector configuration determines the direction of illumination incident on a photosensitive device. Multiple mask layers include holes which form an interlayer optical path through which radiation reaches a photodetector. The interlayer optical path provides a selected nominal maximum signal angle and the detector senses when radiation is received at or near that angle. In one embodiment, three holes in three metallization layers provide an arbitrarily narrow interlayer optical path with improved angular detection relative to that provided by two holes. An illumination direction-sensing array may use multiple instances of the detector configuration. The detector configuration may provide enhanced utility and economy by being adapted to use only those fabrication steps used for fabricating other primary circuits on an IC.

Abstract: An electrode for a memory material of a phase change memory device is disclosed. The electrode includes a first layer adhered to the memory material, the first layer including a nitride (ANx), where A is one of titanium (Ti) and tungsten (W) and x greater than zero, but is less than 1.0, and a second layer adhered to the first layer, the second layer including a nitride (ANy), where y is greater than or equal to 1.0. The multiple layer electrode allows the first layer to better adhere to chalcogenide based memory material, such as GST, than for example, stoichiometric TiN or WN, which prevents delamination. A phase change memory device and method are also disclosed.

Abstract: A nitride-based semiconductor laser device capable of elongating the life thereof is obtained. This nitride-based semiconductor laser device comprises a first cladding layer consisting of a first conductivity type nitride-based semiconductor, an emission layer, formed on the first cladding layer, consisting of a nitride-based semiconductor and a second cladding layer, formed on the emission layer, consisting of a second conductivity type nitride-based semiconductor, while the emission layer includes an active layer emitting light, a light guiding layer for confining light and a carrier blocking layer, arranged between the active layer and the light guiding layer, having a larger band gap than the light guiding layer.

Abstract: A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region.

Abstract: A method of driving a solid-state imaging device using a 4 phase driving method, a 3 phase driving method or a 6 phase driving method. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is used. Two shunt wirings extending in a horizontal direction are formed on the first transfer electrodes connected in a horizontal direction and, for example, four-phase transfer pulses are supplied to first transfer electrodes and second transfer electrodes on transfer channels through low-resistance shunt wirings extending in the horizontal direction.

Abstract: A semiconductor light emitting device can be configured to prevent diffusion migration of components constituting a linear electrode. The semiconductor light emitting device can include a substrate, at least one semiconductor layer formed on the substrate and having a topmost semiconductor layer, a pad electrode formed from a plurality of layers provided on the topmost semiconductor layer, and a linear electrode provided on the topmost semiconductor layer. The linear electrode can be configured to overlap the topmost semiconductor layer except for an area occupied by the pad electrode. The linear electrode can also be configured to make contact with part of the pad electrode, and form an ohmic contact with the topmost semiconductor layer. The pad electrode can include, as one of the plurality of layers, a barrier metal layer that covers part of or all of an upper surface and/or a sidewall of the linear electrode at a contact area between the linear electrode and the pad electrode.

Abstract: An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.

Abstract: A Ti film is pattern-formed on a desired portion on a silicon substrate, and a Co film is formed on the substrate so as to cover the Ti film. CNTs are formed only on a portion, under which the Ti film is formed, of the surface of the Co film at approximately 600° C. by a thermal CVD method. The length of the CNT can be controlled by adjusting the thickness of the Ti film.

Abstract: An electronic device requires an electronic component to be mounted for the purpose of static shielding. The mounting of such an electronic component raises a problem of avoiding thermal stresses and cracks generated due to the difference between the coefficients of linear expansion of component materials. A positioning recess, a joining-substance thickness ensuring recess, a joining-substance thickness ensuring projection, etc. are formed in a combined manner in an electronic component mount portion of each of leads, whereby spreading of cracks generated in the joining substance can be suppressed and reliability can be improved. Filling a sealing material so as to seal and restrain the electronic component mounted in the electronic component mount portion without leaving voids contributes to further suppressing spreading of cracks generated in the joining substance and ensuring more improved reliability of the joining substance.

Abstract: A method of producing a functional device comprising an electrode layer provided as an upper layer of a layer containing an organic material, the layer being as a functional layer, wherein a step of patterning the electrode layer comprises a high speed etching step of etching the electrode layer at a rate of 10 nm/min or more.