Abstract: Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer.

Abstract: A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal is suppressed. a logic chip is directly connected to a DRAM, therefore, it is possible to suppress an increase of load capacitance caused by interconnects, and securing a wide bus width by a multiple pin connection. As a result, it becomes possible to enhance performance of the semiconductor device upon suppressing delay of information transmission from the logic chip to the DRAM.

Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

Abstract: A solder, in particular a thin-film solder, for joining microelectromechanical components, wherein the solder is a eutectic mixture of gold and bismuth. Components and devices joined by a solder of this type are also disclosed, in addition to processes for producing such components or devices.

Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the insulation film without being in contact with the plural diffusion layer patterns and to pass through the insulation film and the semiconductor substrate. Further disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the diffusion layer pattern without being in contact with the insulation film and to pass through the diffusion layer pattern and the semiconductor substrate.

Abstract: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.

Abstract: In a semiconductor device having a plurality of thin film transistors and matrix wiring lines formed on a substrate, the matrix wiring lines are electrically connected via resistors in order to prevent electrostatic destructions during a panel manufacture process and improve a manufacture yield.

Abstract: A thin film transistor (TFT) substrate includes a glass substrate, a thin film transistor, an electrode pad, and a conductive bump. The TFT and the electrode pad are formed on the glass substrate, and the electrode pad is used for electrically connecting with the thin film transistor. The conductive bump includes several insulating bumps and a conductive layer. The insulating bumps are formed on the electrode pad dividedly, and the conductive layer covers the top surfaces of the insulating bumps, the inward surfaces of the insulating bumps, and the electrode pad between the insulating bumps for electrically connecting with the electrode pad. The outward side surfaces of the insulating bumps are exposed out of the conductive layer.

Abstract: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer.

Abstract: An electronic device. The device comprises a metalization layer and an integrated circuit chip incorporated into the device wherein the integrated circuit chip is capacitively coupled to the metalization layer. The device comprises a first substrate having the metalization layer formed on the substrate, a cap layer covering at least the entire metalization layer and at least a portion of the first substrate not covered by the metalization layer. The integrated circuit chip is coupled to the first substrate, and is placed in proximity and in non-physical contact with the metalization layer. A conductive layer is attached to the integrated circuit chip. The conductive layer has at least a portion placed in a non-physical contact with the metalization layer. The integrated circuit chip is capacitively coupled to the metalization layer through the conductive layer and the metalization layer.

Abstract: In a disclosed COC type semiconductor device, a bump electrode (21) of a second semiconductor chip (2) is joined to a first semiconductor chip (1) having a bump electrode (11) formed thereon. The bump electrodes (11) and (21) of the respective first and second semiconductor chips (1) and (2) are both made of first metal such as Au having a relatively high melting point, while a joining portion of these bump electrodes (11) and (21) is formed of an alloy layer (3) of the first metal and second metal, which second metal is made of such a material that can melt at a lower temperature than the melting point of the first metal to be alloyed with it. As a result, in the COC type semiconductor device, when interconnecting a plurality of semiconductor chips, their electrode terminals can be joined to each other without deteriorating the properties of these chips owing to the high temperature applied thereon.

Abstract: Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.

Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.

Abstract: A glass-sealed type semiconductor device has Dumet electrodes, a glass sealing member, and a semiconductor element tightly sealed in a cavity constituted by the Dumet electrodes and the glass sealing member. The semiconductor element is constituted by a Schottky barrier diode. External leads serving as external terminals of the semiconductor device are connected to the Dumet electrodes, respectively. The Dumet electrodes have core portions comprised of a nickel-iron alloy, copper layer formed on the outer peripheries of the core portions, and copper oxide layers formed on the outer surfaces of the copper layers, respectively. The ratios of the copper layers are 20 wt % or more each.

Abstract: A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a carrier substrate of the semiconductor device assembly. The conductive traces may be carried upon a single surface of the routing element substrate, be carried internally by the routing element substrate, or include externally and internally carried portions. The routing element may also include a contact pad positioned at each end of each conductive trace thereof to facilitate electrical connection of each conductive trace to a corresponding terminal of the substrate or to a corresponding bond pad of a semiconductor device of the multichip module. Multichip modules are also disclosed, as are methods for designing the routing element and methods in which the routing element is used.

Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

Abstract: A solid-state imaging device capable of reducing an eclipse (blocking) of an incident light at a circumferential portion of a light receiving portion and realizing a larger angle of view and high-speed driving. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is adopted. Two shunt wirings extending in a horizontal direction are formed on the first transfer electrodes connected in a horizontal direction and, for example, four-phase transfer pulses are supplied to first transfer electrodes and second transfer electrodes on transfer channels through low-resistance shunt wirings extending in the horizontal direction.

Abstract: A GaN-based LED structure is provided so that the brightness and luminous efficiency of the GaN-based LED are enhanced effectively. The greatest difference between the GaN-based LEDs according to the invention and the prior arts lies in the addition of a masking buffer layer and a roughened contact layer on top of the masking buffer layer. The masking buffer layer contains randomly distributed clusters made of a group-IV nitride SixNy (x,y?1), a group-II nitride MgwNz (w,z?1), or a group-III nitride AlsIntGa1?s?tN (0?s,t<1, s+t?1) heavily doped with at least a group-II and group-IV element such as Mg and Si. The roughened contact layer, made of AluInvGa1?u?vN (0?u,v<1, u+v?1), starts from the top surface of an underlying second contact layer not covered by the masking buffer layer's clusters, and then grows upward until it passes (but does not cover) the clusters of the masking buffer layer for an appropriate distance.

Abstract: A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, has all of the source/drain contacts away from the fins as much as reasonably possible. The gate contacts extend upward from the top surface of the elevated semiconductor portion. The gate also extends upward from the top surface of the elevated semiconductor portion. The contacts are located between the fins where the gate is below the height of the elevated semiconductor portion so the contacts are as far as reasonably possible from the gate, thereby reducing gate to drain capacitance and providing additional assistance to alignment tolerance.