Patents Examined by Benjamin P. Sandvik
  • Patent number: 10734450
    Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Rie Sim, Gwan-Hyeob Koh, Dae-Hwan Kang
  • Patent number: 10734487
    Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first insulator over a substrate, an oxide over the first insulator, a second insulator over the oxide, a conductor overlapping with the oxide with the second insulator therebetween, a third insulator in contact with a top surface of the oxide, a fourth insulator in contact with a top surface of the third insulator, a side surface of the second insulator, and a side surface of the conductor, and a fifth insulator in contact with a side surface of the fourth insulator, a side surface of the third insulator, and the top surface of the oxide. The third insulator has a lower oxygen permeability than the fourth insulator.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Komagata, Naoki Okuno, Yutaka Okazaki, Hiroshi Fujiki
  • Patent number: 10732610
    Abstract: An information processing terminal according to an exemplary embodiment of the present invention acquires information about an expendable part including a modeling material to be used in modeling by a control apparatus configured to model a three-dimensional object, and displays information about the number of objects that can be modeled in a form corresponding to a predetermined object by the control apparatus with the amount of the modeling material remaining in the expendable part corresponding to the acquired information and also displays information specifying the shape and size of the predetermined object.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: August 4, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Makoto Dohi
  • Patent number: 10727171
    Abstract: A lead frame includes a plurality of leads formed from a metal plate having a front side and a back side, a first resin member, and a second resin member. The leads have side faces thereof fixed with the first resin member. Faces serving as internal connectors of the leads are uncovered on the side of the front-side surface of the first resin member, and faces serving as external connectors of the leads are uncovered on the side of the back-side surface of the first resin member. The second resin member is formed on the front-side surface of the first resin member to be at a level higher than the faces serving as the internal connectors, and has openings for leaving the faces serving as the internal connectors uncovered.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 28, 2020
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventors: Kaoru Hishiki, Ryouichi Yoshimoto, Ichinori Iidani
  • Patent number: 10720360
    Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
  • Patent number: 10714519
    Abstract: Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 14, 2020
    Assignee: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano
  • Patent number: 10695868
    Abstract: Laser hybrid welding systems adapted to identify and/or fix a weld defect occurring during a laser hybrid welding process are provided. Embodiments of the laser hybrid welding system may include one or more devices that provide feedback to a controller regarding one or more weld parameters. One embodiment of the laser hybrid welding system includes sensors that are adapted to measure the weld voltage and/or amperage during the welding process and transmit the acquired data to the controller for processing. Another embodiment of the laser hybrid welding system includes a lead camera and a lag camera that film an area directly in front of the weld location and directly behind the weld location.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 30, 2020
    Assignee: Illinois Tool Works Inc.
    Inventor: Bruce Patrick Albrecht
  • Patent number: 10698388
    Abstract: A field device, which measures a physical quantity in a plant or processes the physical quantity, includes: an instruction unit configured to output a verification execution instruction signal for instructing execution of verification of the field device; an operation verifying unit configured to verify an operation of at least one element of the field device in response to the verification execution instruction signal and to verify an operation of the field device based on the verification result; and an output unit configured to output the verification result which is a result of verification of the operation by the operation verifying unit.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 30, 2020
    Assignee: Yokogawa Electric Corporation
    Inventors: Ikuhiko Ishikawa, Toru Shimura, Daisuke Harigane, Shinnosuke Yoshida
  • Patent number: 10691093
    Abstract: Devices, systems, and methods for controller programming migration automation are described herein. One device includes instructions executable to receive controller programming information associated with a first controller of a building system, wherein the received controller programming information is of a first information type, convert the received controller programming information to a second information type associated with a second controller of the building system, based, at least in part, on a set of conversion rules particular to the first controller and the second controller, and generate a report including information associated with the conversion.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: June 23, 2020
    Assignee: Honeywell International Inc.
    Inventors: Jayaprakash Meruva, Nagesh Narayanappa, Amruth Hiremath, Andrew David Halford, Cary Leen, Roy Alan Kolasa
  • Patent number: 10692010
    Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: June 23, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekenas
  • Patent number: 10685957
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 10686161
    Abstract: A display device includes a display panel, a first film, and a second film. The display panel includes a light emitter to emit light including display information, a first surface, and a second surface opposite to the first surface. The light passes through a second surface. The first film is on the first surface of the display panel. The second film is on the second surface of the display panel. The display panel includes a side surface that connects the first surface and the second surface. A side surface of the second film protrudes outwardly more than a side surface of the first film with respect to the side surface of the display panel. The side surface of the second film is inclined at an angle greater than about 90 degrees with respect to the second surface.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Minsoo Kang, Gwangjae Seo, Myeongseok Jeong, Yongsik Heo, Kyoungil Min, Junshik Park, Taehyun Sung, Hyungu Lee
  • Patent number: 10686102
    Abstract: The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10, and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10. The first resin molding 40 has the recess 40c comprising the bottom surface 40a and the side surface 40b formed therein, and the second resin molding 50 is placed in the recess 40c.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: June 16, 2020
    Assignee: Nichia Corporation
    Inventors: Masafumi Kuramoto, Tomohisa Kishimoto
  • Patent number: 10686107
    Abstract: Light emitter devices, components and methods are disclosed. In one aspect, a light emitter component of a light emitter device is disclosed. The light emitter component can include a silver (Ag) portion at least partially disposed over a surface of the component. The component can further include a protective layer at least partially disposed over the Ag portion, the protective layer at least partially including an organic barrier material that increases or improves chemical resistance of the Ag portion. In some aspects, the protective layer includes a polyxylylene (e.g., poly(p-xylylene), a substituted poly(p-xylylene), a fluorocarbon containing poly(p-xylylene), and/or any other polymer prepared from a xylylene and/or comprising —CH2—(C6H4)—CH2— based repeating units. In some aspects, the protective layer includes Parylene.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: June 16, 2020
    Assignee: Cree, Inc.
    Inventors: Shaow B. D. Lin, Peter Scott Andrews
  • Patent number: 10680020
    Abstract: A peeling method at low cost with high mass productivity is provided. A resin layer having a thickness greater than or equal to 0.1 ?m and less than or equal to 3 ?m is formed over a formation substrate using a photosensitive and thermosetting material, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, the resin layer is irradiated with light using a linear laser device, and the transistor and the formation substrate are separated from each other. A first region and a second region which is thinner than the first region or an opening can be formed in the resin layer. In the case of forming a conductive layer functioning as an external connection terminal or the like to overlap with the second region or the opening of the resin layer, the conductive layer is exposed.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 9, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Satoru Idojiri, Kenichi Okazaki, Hiroki Adachi, Daisuke Kubota
  • Patent number: 10676554
    Abstract: A polymer compound comprising a repeating unit having at least one group selected from the group consisting of a blocked isocyanato group and a blocked isothiocyanato group, a repeating unit having at least one group selected from the group consisting of a hydroxy group and a carboxy group and a repeating unit represented by the following formula (1), wherein the content of the repeating unit having at least one group selected from the group consisting of a blocked isocyanato group and a blocked isothiocyanato group in the polymer compound is 1% by mol or more and 30% by mol or less when the total content of all repeating units contained in the above-described polymer compound is taken as 100% by mol: in the formula (1), R2, R2 and R3 each independently represent a hydrogen atom or a methyl group.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 9, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Yuki Yokoi
  • Patent number: 10680045
    Abstract: An organic light emitting display device includes: an insulating layer; first electrodes on the insulating layer and spaced from each other by a gap; an organic light emitting layer on the first electrodes; and a second electrode on the organic light emitting layer, wherein the insulating layer includes a trench between the first electrodes, wherein the organic light emitting layer includes a first stack on the first electrodes, a charge generating layer on the first stack, and a second stack on the charge generating layer, wherein each of the first and second stacks includes a hole transporting layer, at least one emitting material layer and an electron transporting layer, and wherein the first stack has a discontinuous portion in the trench.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: June 9, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Min Baik, Joon-Young Heo
  • Patent number: 10672718
    Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 2, 2020
    Assignee: Georgia Tech Research Corporation
    Inventors: Venkatesh Sundaram, Fuhan Liu, Rao R. Tummala, Vijay Sukumaran, Vivek Sridharan, Qiao Chen
  • Patent number: 10672915
    Abstract: An object is to improve reliability of a light-emitting device. A light-emitting device has a driver circuit portion including a transistor for a driver circuit and a pixel portion including a transistor for a pixel over one substrate. The transistor for the driver circuit and the transistor for the pixel are inverted staggered transistors each including an oxide semiconductor layer in contact with part of an oxide insulating layer. In the pixel portion, a color filter layer and a light-emitting element are provided over the oxide insulating layer. In the transistor for the driver circuit, a conductive layer overlapping with a gate electrode layer and the oxide semiconductor layer is provided over the oxide insulating layer. The gate electrode layer, a source electrode layer, and a drain electrode layer are formed using metal conductive films.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama
  • Patent number: 10665612
    Abstract: A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 26, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki