Patents Examined by Benjamin P. Sandvik
  • Patent number: 11930638
    Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moorym Choi, Jungtae Sung, Sanghee Yoon, Wooyong Jeon, Junyoung Choi, Yoonjo Hwang
  • Patent number: 11916098
    Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 27, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Wei Luo, Chieh-Pin Chang, Kai-Yi Huang, Ta-Hsun Yeh
  • Patent number: 11910613
    Abstract: A semiconductor memory device includes a mold structure including a plurality of wordlines on a front side of a first substrate, and a string selection line and a stopper line on the plurality of wordlines. A channel structure extends in a vertical direction to penetrate the mold structure. A block separation area extends in a first direction to cut the mold structure. A protective structure is interposed between the block separation area and the stopper line and not between the block separation area and the string selection line and not between the block separation area and the plurality of wordlines. A string separation structure extends in the first direction to cut the string selection line and the stopper line. A bitline extends in a second direction on the mold structure. A bitline contact connects the channel structure and the bitline.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Joon Ryu, Hee Suk Kim, Jeong Yong Sung, Jee Hoon Han
  • Patent number: 11906853
    Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: February 20, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xue Dong, Liwei Liu, Xinxing Wang, Yun Sik Im, Hyun Sic Choi, Jaegeon You, Yinglong Huang, Heecheol Kim
  • Patent number: 11897760
    Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: February 13, 2024
    Assignee: X-Celeprint Limited
    Inventors: Ronald S. Cok, Raja Fazan Gul, António José Marques Trindade
  • Patent number: 11901264
    Abstract: Embodiments disclosed herein include electronic packages with chocked flow cooling. In an embodiment, an electronic package may comprise a package substrate, a die electrically and mechanically coupled to the package substrate, and a lid over the die. In an embodiment, the lid has a first opening and a second opening that is opposite from the first opening. In an embodiment, the electronic package may further comprise a coolant plate covering the first opening. In an embodiment, the coolant plate comprises a first surface facing away from the die and a second surface facing the die, and a plurality of vents from the first surface to the second surface. In an embodiment, the first openings of the plurality of vents have a first dimension and second openings of the plurality of vents have a second dimension that is smaller than the first dimension.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 13, 2024
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Mark Forsnes, Yuhong Cai, Florence Pon, Yi Xu
  • Patent number: 11901186
    Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: February 13, 2024
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of Singapore
    Inventors: Li Zhang, Kwang Hong Lee, Keith Cheng Yeow Ng, Kenneth Eng Kian Lee, Eugene A. Fitzgerald, Soo Jin Chua, Chuan Seng Tan
  • Patent number: 11894470
    Abstract: An optical sensor includes a substrate, a photoelectric element disposed on the substrate and that includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a barrier layer disposed on the second electrode, an insulating layer that covers the photoelectric element and the barrier layer, and a bias electrode disposed on the insulating layer and electrically connected to the second electrode. The barrier layer is spaced apart from the first electrode.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki June Lee, Jung Ha Son, Tae Sung Kim, Jae Ik Lim, Hyun Min Cho
  • Patent number: 11894477
    Abstract: An electrical device includes a substrate with a compressive layer, a neutral stress buffer layer and a tensile stress compensation layer. The stress buffer layer and the stress compensation layer may each be formed with aluminum nitride using different processing parameters to provide a different intrinsic stress value for each layer. The aluminum nitride tensile layer is configured to counteract stresses from the compressive layer in the device to thereby control an amount of substrate bow in the device. This is useful for protecting fragile materials in the device, such as mercury cadmium telluride. The aluminum nitride stress compensation layer also can compensate for forces, such as due to CTE mismatches, to protect the fragile layer. The device may include temperature-sensitive materials, and the aluminum nitride stress compensation layer or stress buffer layer may be formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: February 6, 2024
    Assignee: Raytheon Company
    Inventors: Andrew Clarke, Emily Thomson, Michael Rondon
  • Patent number: 11884537
    Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: January 30, 2024
    Assignee: X-Celeprint Limited
    Inventors: Ronald S. Cok, Raja Fazan Gul, António José Marques Trindade
  • Patent number: 11888081
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Yi Wu, Chang Chin Tsai, Bo-Yu Huang, Ying-Chung Chen
  • Patent number: 11885991
    Abstract: A display device includes a display panel including a first array of light emitters having a first spacing in a first emission region of the display panel and a second array of light emitters having a second spacing in a second emission region of the display panel. The second spacing is distinct from the first spacing. The display device includes an optical filter including a first filter region and a second filter region. The first filter region changes distribution of first light from the first array of light emitters impinging on the first filter region so that the first light has a first distribution after passing through the first filter region. The second filter region changes distribution of second light from the second array of light emitters impinging on the second filter region so that the second light has a second distribution after passing through the second filter region.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 30, 2024
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Andrew John Ouderkirk, James Ronald Bonar, Jasmine Soria Sears
  • Patent number: 11889767
    Abstract: A multilayer piezoelectric ceramic is such that: its piezoelectric ceramic layers do not contain lead as a constituent element, and have a perovskite compound expressed by the composition formula LixNayK1-x-yNbO3 (where 0.02<x?0.1, 0.02<x+y?1), as the primary component; and the internal electrode layers are constituted by a metal containing silver by 80 percent by mass or more, and contain ceramic grains containing the same elements found in the primary component. The multilayer piezoelectric element has a long lifespan, and whose internal electrode layers have a high content percentage of silver.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: January 30, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Gouki Watanabe, Ryo Ito, Takayuki Goto, Hiroyuki Shimizu, Sumiaki Kishimoto
  • Patent number: 11889765
    Abstract: A MEMS device is provided that includes a semiconductor substrate including a main surface extending perpendicular to a first direction and a side surface extending on a plane parallel to the first direction and to a second direction that is perpendicular to the first direction. At least one cantilevered member protrudes from the side surface of the semiconductor substrate along a third direction that is perpendicular to the first and second directions. The at least one cantilevered member includes a body portion that includes a piezoelectric material. The body portion has a length along the third direction, a height along the first direction and a width along the second direction, and the height is greater than the width. The at least one cantilevered member is configured to vibrate by lateral bending along a direction perpendicular to the first direction.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 30, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Gianluca Longoni, Luca Seghizzi
  • Patent number: 11884536
    Abstract: Provided are an electrical interconnection structure, an electronic apparatus and manufacturing methods therefor, which can provide a reliable electrical interconnection structure between the MEMS apparatus and an external circuit while sealing and encapsulating the MEMS device. The electrical interconnection structure includes: a bonding metal; a first dielectric layer and a second dielectric layer. The first dielectric layer includes a first through hole penetrating the first dielectric layer and exposing the bonding metal. The first through hole is filled with a first conductive material electrically connected to the bonding metal. The second dielectric layer includes a second through hole. An orthographic projection of second conductive material in the second through hole covers an orthographic projection of first conductive material in the first through hole onto the plane of the base.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 30, 2024
    Assignee: AAC TECHNOLOGIES PTE. LTD.
    Inventors: Bharadwaja S.N. Shrowthi, Jeffrey Crosswell Maling
  • Patent number: 11884538
    Abstract: A sensor device includes a first and second Micro-Electro-Mechanical (MEM) structures. The first MEM structure includes a first heating element on a first layer of the first MEM structure. The first heating element includes an input adapted to receive an input signal. The first MEM structure also includes a first temperature sensing element on a second layer of the first MEM structure. The second MEM structure includes a second heating element on a first layer of the second MEM structure and a second temperature sensing element on a second layer of the second MEM structure. An output circuit has a first input coupled to the first temperature sensing element and a second input coupled to the second temperature sensing element.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: January 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marco Corsi, Barry Jon Male
  • Patent number: 11887900
    Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
  • Patent number: 11876035
    Abstract: The present description concerns an electronic chip (202) formed on top and inside of a semiconductor substrate including, one the side of a first surface (202B), at least one active component and, on the side of a second surface (202T) opposite to the first surface, at least one channel for the circulation of a liquid intended to cool the chip.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: January 16, 2024
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventor: Gilles Simon
  • Patent number: 11877500
    Abstract: A mask assembly includes a mask and a blocking stick. The mask includes a pattern region formed therein with openings and extends in a first direction. The blocking stick is disposed under the mask and overlaps a first side portion of the mask. The mask further includes dummy opening regions and opening regions. The dummy opening regions are arranged in the first direction in the first side portion of the mask, and are formed therein with openings. The opening regions are arranged in the first direction in a second side portion which is opposite to the first side portion of the mask and correspond to the dummy opening regions, respectively. The number of the openings per a unit area in each of the dummy opening region and the opening region is smaller than the number of the openings per a unit area in the pattern region.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sanghoon Kim, Jongbum Kim, Yeonju Kang, Jongsung Park, Sangshin Lee, Seungjin Lee, Eunjoung Jung
  • Patent number: 11869766
    Abstract: A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Yu-Ming Lin