Patents Examined by Benjamin P. Sandvik
  • Patent number: 12219697
    Abstract: A display assembly includes: a display panel including a driving circuit and a first pad; and a flexible circuit board including a flexible base plate, a first wiring layer and a first reinforcement plate. The first wiring layer is on the flexible base plate and includes a main routing portion and a second pad, and the first reinforcement plate is on a side of the first wiring layer distal to the flexible base plate; an orthogonal projection of the main routing portion on the flexible base plate is within an orthogonal projection of the first reinforcement plate on the flexible base plate; the second pad is connected to the main routing portion, and is electrically connected to the first pad; the first reinforcement plate is outside the display panel and has a first edge proximal to the display panel The first edge includes convex and concave portions alternately arranged.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: February 4, 2025
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiao Bai, Shengji Yang, Kuanta Huang, Pengcheng Lu
  • Patent number: 12209012
    Abstract: According to an example aspect of the present invention, there is provided a wafer level package for a device, the package comprising: a first substrate and a second substrate, a sealing structure comprising a seal ring and a bonding layer between the first substrate and the second substrate, and a lateral electrical connection line on a surface of the first substrate, which lateral electrical connection line extends through the seal ring for creating an electrical connection between the device inside the package and an electrical circuit outside the package.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 28, 2025
    Assignee: Teknologian tutkimuskeskus VTT Oy
    Inventor: Jae-Wung Lee
  • Patent number: 12207507
    Abstract: Disclosed are a display substrate, a display panel and a display apparatus. The display substrate includes a base substrate; a plurality of read signal lines, extending on the base substrate in a first direction; a plurality of display signal lines, extending on the base substrate in a second direction, the second direction intersects with the first direction, the plurality of display signal lines and the plurality of read signal lines are arranged on different layers, there is an overlapped region between an orthographic projection of the plurality of display signal lines on the base substrate and an orthographic projection of the plurality of read signal lines; and a shielding layer, located between a layer where the plurality of read signal lines are and a layer where the plurality of display signal lines are, an orthographic projection of the shielding layer on the base substrate at least covers the overlapped region.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: January 21, 2025
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Fangyuan Zhao, Yangbing Li, Peng Jia, Yunke Qin, Lei Wang
  • Patent number: 12199199
    Abstract: An optical sensor includes a substrate, a photoelectric element disposed on the substrate and that includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a barrier layer disposed on the second electrode, an insulating layer that covers the photoelectric element and the barrier layer, and a bias electrode disposed on the insulating layer and electrically connected to the second electrode. The barrier layer is spaced apart from the first electrode.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: January 14, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki June Lee, Jung Ha Son, Tae Sung Kim, Jae Ik Lim, Hyun Min Cho
  • Patent number: 12200971
    Abstract: A display device includes a substrate including a first display area and a second display area, first pixels disposed on the substrate in the first display area, a functional module disposed below the substrate in the second display area, and a light block layer disposed on the functional module. The light block layer includes patterns disposed in a matrix in the second display area. The second display area includes a transmission area as an area in the second display area not including the light block layer. Each of the patterns include a main part having a substantially rectangular shape with substantially rounded corners and line parts substantially curved away from the main part.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: January 14, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Kyung Hyun Choi
  • Patent number: 12200938
    Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: January 14, 2025
    Inventors: Haitao Liu, Kamal M. Karda, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu
  • Patent number: 12183585
    Abstract: Provided is a manufacturing method of a semiconductor structure, including: providing a substrate; forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions; forming several discrete bitlines on the active regions; forming a sacrificial layer between adjacent bitlines; forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact structures. The embodiment of the present disclosure is beneficial to reducing the manufacturing cost of the semiconductor structure.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: December 31, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kui Zhang, Zhan Ying
  • Patent number: 12176214
    Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Rahim Kasim, Manish Chandhok, Florian Gstrein
  • Patent number: 12170228
    Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
  • Patent number: 12162747
    Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: December 10, 2024
    Assignee: X-Celeprint Limited
    Inventors: Ronald S. Cok, Raja Fazan Gul, António José Marques Trindade
  • Patent number: 12167664
    Abstract: A display panel and a preparation method therefor, and a display apparatus. The display panel comprises: a display region and a bezel region surrounding the display region; a barrier structure, located in the bezel region and arranged on one side of the base substrate, surrounding the display region; a touch-control electrode lead, comprising a first metal lead and a metal connection bridge which are electrically connected; said first metal lead is arranged on the upper side of said barrier structure; the first metal lead extends from the display region to the bezel region and is located on the side of the barrier structure facing the display region; said metal connection bridge is located in the bezel region; the metal connection bridge is arranged between the base substrate and the surface of the barrier structure on the side away from the base substrate.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: December 10, 2024
    Assignees: Beijing BOE Technology Development Co., Ltd., Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yangsheng Liu, Xuwu Hu, Hwang Kim, Wei Lin
  • Patent number: 12157664
    Abstract: In one or more embodiments, an apparatus generally comprises a microelectromechanical system (MEMS) module comprising a plurality of air movement cells and a power unit operable to control the plurality of air movement cells, and a housing configured for slidably receiving the MEMS module and positioning the MEMS module adjacent to a heat generating component of a network device. The MEMS module is operable to dissipate heat from the heat generating component and is configured for online installation and removal during operation of the heat generating component.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: December 3, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: Joel Richard Goergen
  • Patent number: 12154953
    Abstract: Disclosed is a method for manufacturing a contact hole, a semiconductor structure and electronic equipment. The method includes: forming a mask layer on an upper end face of a first oxide layer of the semiconductor structure, and exposing a pattern of a target contact hole on the mask layer; exposing a portion, corresponding to a target contact hole, of an upper end face of a contact layer and a portion, corresponding to the target contact hole, of an upper end face of an upper layer structure; depositing a second insulation layer on an etched surface, and depositing a second oxide layer on the second insulation layer; and removing portions, above the upper end face of the first oxide layer, of the second insulation layer and the second oxide layer, and removing a part of the contact layer, and exposing an upper end face of a zeroth layer contact.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: November 26, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Ran Li, Ching-Lun Ma, Leilei Duan, Xinru Han
  • Patent number: 12155026
    Abstract: High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: November 26, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Martin F. Schubert
  • Patent number: 12145839
    Abstract: A MEMS actuator assembly package features a number of drop test resistant mechanisms is disclosed. These mechanisms are used to decelerate and finally stops the heavy load of the image sensor attached to the MEMS actuators along all six directions of the in-plane and out-of-plane axes (±x, ±y, ±z). The MEMS actuator assembly package comprises first and second sets of flexible stoppers attached to the MEMS actuator along with a set of hard stoppers that engage in a sequential manner with the moving mass of the loaded actuator to decelerate it, bringing it to a complete stop when exposed to mechanical shock along the four directions of the in-plane axes (x and y). When the assembly package is exposed along the positive and negative direction of the z-axis, the moving mass is stopped by features built in the package.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: November 19, 2024
    Inventors: Faez Ba-Tis, Ahmed Galaom, Ali Banss, Hui Zuo
  • Patent number: 12148746
    Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Hsu, Bo-Ting Chen, Jam-Wem Lee
  • Patent number: 12148679
    Abstract: A semiconductor device, a semiconductor package, and a method of manufacturing the same are provided. The semiconductor device includes an electronic component, a first thermal conductive layer, a second thermal conductive layer, and a solderable element. The first thermal conductive layer is disposed adjacent to a surface of the electronic component. The second thermal conductive layer is disposed on the first thermal conductive layer and exposes a portion of the first thermal conductive layer. The solderable element is disposed on the second thermal conductive layer.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Tun-Ching Pi
  • Patent number: 12148631
    Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 19, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kazunaga Onishi, Takashi Masuzawa, Hiromichi Gohara
  • Patent number: 12134556
    Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: November 5, 2024
    Assignees: STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.
    Inventors: Enri Duqi, Lorenzo Baldo, Paolo Ferrari, Benedetto Vigna, Flavio Francesco Villa, Laura Maria Castoldi, Ilaria Gelmi
  • Patent number: 12137581
    Abstract: One aspect of the present disclosure is an organic EL display, which includes a large number of light emitting elements that emit light when an organic substance is energized. The organic EL display has a display unit configured to display an image by emitting light generated by a large number of light emitting elements from a display surface, and a peripheral member arranged on the same surface as the display surface so as to surround the periphery of the display unit and made of a material having a light absorption rate that matches the light absorption rate of the display unit when no light is emitted.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: November 5, 2024
    Assignee: DENSO CORPORATION
    Inventor: Seigo Tane