Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Abstract: An image sensing device includes a first subpixel block, a second subpixel block, a first conversion gain transistor, and a second conversion gain transistor. The first subpixel block includes a first floating diffusion region and a plurality of unit pixels sharing the first floating diffusion region. The second subpixel block includes a second floating diffusion region coupled to the first floating diffusion region and a plurality of unit pixels sharing the second floating diffusion region. The first conversion gain transistor includes a first impurity region coupled to the first and second floating diffusion regions and a second impurity region coupled to a first conversion gain capacitor. The second conversion gain transistor includes a third impurity region coupled to the second impurity region of the first conversion gain transistor and a fourth impurity region coupled to a second conversion gain capacitor.

Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

Abstract: According to one embodiment, a photoelectric conversion element includes a first conductive layer, a second conductive layer, a photoelectric conversion layer located between the first conductive layer and the second conductive layer. The photoelectric conversion layer includes Sn and Pb. The photoelectric conversion layer includes a first partial region, a second partial region between the first partial region and the second conductive layer, and a third partial region between the second partial region and the second conductive layer. The first partial region includes a first Sn concentration and a first Pb concentration. The second partial region includes at least one of a second Sn concentration or a second Pb concentration. The second Sn concentration is less than the first Sn concentration. The second Pb concentration is greater than the first Pb concentration. The third partial region includes Sn, oxygen, and Pb.

Abstract: A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Abstract: A display device includes: a display area including a plurality of pixels; a first peripheral area disposed at one side of the display area; and a second peripheral area disposed at the opposite side of the display area, wherein a first column spacer is disposed in the display area, a second column spacer is disposed in the first peripheral area, and a third column spacer is disposed in the second peripheral area. The patterns of an exposure mask utilized in the first peripheral area in which the second column spacer is disposed and the second peripheral area in which the third column spacer is disposed may be different from each other.

Abstract: Various embodiments include a heat sink comprising: a base plate with an assembly surface for an electronic component; and a cooling structure bonded to the base plate increasing a surface area of the heat sink. The base plate comprises a metal-ceramic composite with a ceramic phase and a metallic phase. The cooling structure comprises a metal. A bond between the cooling structure and the base plate consists of a purely metallic bond between the cooling structure and the metallic phase of the base plate.

Abstract: A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

Abstract: An array substrate and a fabrication method thereof, an array substrate motherboard, and a display device are disclosed. The array substrate includes a display region and a bonding region outside the display region. The array substrate further includes: a bonding electrode, located in the bonding region and spaced apart from an outer edge of the bonding region; and an electrostatic barrier line, the electrostatic barrier line has one end electrically connected with the bonding electrode, and the other end extends to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is greater than resistivity of the bonding electrode.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Abstract: A display device includes a display panel, a first film, and a polarizing film. The display panel includes a first surface, a second surface opposite to the first surface, and a side surface. The first film is beneath the first surface of the display panel. The polarizing film is on the second surface of the display panel. The polarizing film has a haze area including a yellow area extending along an edge of the polarizing film in a plan view.

Abstract: A semiconductor device includes: a semiconductor element; a submount on which the semiconductor element is mounted, wherein the submount has a first surface on which the semiconductor element is mounted, a second surface located on a side opposite the first surface, and a lateral surface located between the first surface and the second surface, and wherein the submount comprises: a groove located at the second surface, a heat dissipation portion located at the second surface, and an electrode pattern located at the first surface; a package substrate on which the submount is mounted; a first joint member that physically joins the heat dissipation portion to the package substrate; and a connection portion located on the side surface, wherein the connection portion electrically connects the electrode pattern and the package substrate, and the connection portion comprises a second joint member.

Abstract: Methods, apparatuses and systems to provide for technology to that includes a first power electronics module including a plurality of first transistors that are diagonally offset from each other, and a second power electronics module stacked on the first power electronics module. The second power electronics module includes second transistors that are diagonally offset from each other. The second transistors are staggered relative to the first transistors.

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.

Abstract: A semiconductor memory device includes a mold structure including a plurality of wordlines on a front side of a first substrate, and a string selection line and a stopper line on the plurality of wordlines. A channel structure extends in a vertical direction to penetrate the mold structure. A block separation area extends in a first direction to cut the mold structure. A protective structure is interposed between the block separation area and the stopper line and not between the block separation area and the string selection line and not between the block separation area and the plurality of wordlines. A string separation structure extends in the first direction to cut the string selection line and the stopper line. A bitline extends in a second direction on the mold structure. A bitline contact connects the channel structure and the bitline.

Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.

Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.

Abstract: Embodiments disclosed herein include electronic packages with chocked flow cooling. In an embodiment, an electronic package may comprise a package substrate, a die electrically and mechanically coupled to the package substrate, and a lid over the die. In an embodiment, the lid has a first opening and a second opening that is opposite from the first opening. In an embodiment, the electronic package may further comprise a coolant plate covering the first opening. In an embodiment, the coolant plate comprises a first surface facing away from the die and a second surface facing the die, and a plurality of vents from the first surface to the second surface. In an embodiment, the first openings of the plurality of vents have a first dimension and second openings of the plurality of vents have a second dimension that is smaller than the first dimension.