Abstract: An optical sensor includes a substrate, a photoelectric element disposed on the substrate and that includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a barrier layer disposed on the second electrode, an insulating layer that covers the photoelectric element and the barrier layer, and a bias electrode disposed on the insulating layer and electrically connected to the second electrode. The barrier layer is spaced apart from the first electrode.

Abstract: An electrical device includes a substrate with a compressive layer, a neutral stress buffer layer and a tensile stress compensation layer. The stress buffer layer and the stress compensation layer may each be formed with aluminum nitride using different processing parameters to provide a different intrinsic stress value for each layer. The aluminum nitride tensile layer is configured to counteract stresses from the compressive layer in the device to thereby control an amount of substrate bow in the device. This is useful for protecting fragile materials in the device, such as mercury cadmium telluride. The aluminum nitride stress compensation layer also can compensate for forces, such as due to CTE mismatches, to protect the fragile layer. The device may include temperature-sensitive materials, and the aluminum nitride stress compensation layer or stress buffer layer may be formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.

Abstract: A display device includes a display panel including a first array of light emitters having a first spacing in a first emission region of the display panel and a second array of light emitters having a second spacing in a second emission region of the display panel. The second spacing is distinct from the first spacing. The display device includes an optical filter including a first filter region and a second filter region. The first filter region changes distribution of first light from the first array of light emitters impinging on the first filter region so that the first light has a first distribution after passing through the first filter region. The second filter region changes distribution of second light from the second array of light emitters impinging on the second filter region so that the second light has a second distribution after passing through the second filter region.

Abstract: A multilayer piezoelectric ceramic is such that: its piezoelectric ceramic layers do not contain lead as a constituent element, and have a perovskite compound expressed by the composition formula LixNayK1-x-yNbO3 (where 0.02<x?0.1, 0.02<x+y?1), as the primary component; and the internal electrode layers are constituted by a metal containing silver by 80 percent by mass or more, and contain ceramic grains containing the same elements found in the primary component. The multilayer piezoelectric element has a long lifespan, and whose internal electrode layers have a high content percentage of silver.

Abstract: A MEMS device is provided that includes a semiconductor substrate including a main surface extending perpendicular to a first direction and a side surface extending on a plane parallel to the first direction and to a second direction that is perpendicular to the first direction. At least one cantilevered member protrudes from the side surface of the semiconductor substrate along a third direction that is perpendicular to the first and second directions. The at least one cantilevered member includes a body portion that includes a piezoelectric material. The body portion has a length along the third direction, a height along the first direction and a width along the second direction, and the height is greater than the width. The at least one cantilevered member is configured to vibrate by lateral bending along a direction perpendicular to the first direction.

Abstract: Provided are an electrical interconnection structure, an electronic apparatus and manufacturing methods therefor, which can provide a reliable electrical interconnection structure between the MEMS apparatus and an external circuit while sealing and encapsulating the MEMS device. The electrical interconnection structure includes: a bonding metal; a first dielectric layer and a second dielectric layer. The first dielectric layer includes a first through hole penetrating the first dielectric layer and exposing the bonding metal. The first through hole is filled with a first conductive material electrically connected to the bonding metal. The second dielectric layer includes a second through hole. An orthographic projection of second conductive material in the second through hole covers an orthographic projection of first conductive material in the first through hole onto the plane of the base.

Abstract: A sensor device includes a first and second Micro-Electro-Mechanical (MEM) structures. The first MEM structure includes a first heating element on a first layer of the first MEM structure. The first heating element includes an input adapted to receive an input signal. The first MEM structure also includes a first temperature sensing element on a second layer of the first MEM structure. The second MEM structure includes a second heating element on a first layer of the second MEM structure and a second temperature sensing element on a second layer of the second MEM structure. An output circuit has a first input coupled to the first temperature sensing element and a second input coupled to the second temperature sensing element.

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

Abstract: The present description concerns an electronic chip (202) formed on top and inside of a semiconductor substrate including, one the side of a first surface (202B), at least one active component and, on the side of a second surface (202T) opposite to the first surface, at least one channel for the circulation of a liquid intended to cool the chip.

Abstract: A mask assembly includes a mask and a blocking stick. The mask includes a pattern region formed therein with openings and extends in a first direction. The blocking stick is disposed under the mask and overlaps a first side portion of the mask. The mask further includes dummy opening regions and opening regions. The dummy opening regions are arranged in the first direction in the first side portion of the mask, and are formed therein with openings. The opening regions are arranged in the first direction in a second side portion which is opposite to the first side portion of the mask and correspond to the dummy opening regions, respectively. The number of the openings per a unit area in each of the dummy opening region and the opening region is smaller than the number of the openings per a unit area in the pattern region.

Abstract: A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.

Abstract: A method for manufacturing a nitride semiconductor device includes: selectively ion-implanting an element that is other than p-type impurities and n-type impurities into a first region in a first primary surface of a gallium nitride layer so as to generate crystal defects in the first region; selectively ion-implanting a p-type impurity into a second region in the gallium nitride layer, the second region being shallower than the first region in a depth direction and being within the first region in a plan view; and thermally treating said gallium nitride layer that has been ion-implanted with said element and said p-type impurity so as to thermally diffuse said p-type impurity in the second region into a third region that is within the first region and that surrounds a bottom and sides of the second region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a first negative capacitance material, and an isolation structure formed over the substrate. The semiconductor device structure includes a gate structure formed over the fin structure, and a source feature and a drain feature formed over the fin structure. An interface between the fin structure and the source feature is lower than a top surface of the isolation structure.

Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

Abstract: Display device and method of manufacturing the display device are provided. According to an exemplary embodiment of the present disclosure, a display device includes a display panel having a display area and a pad area, which is spaced apart from the display area; a protective film disposed on one surface of the display panel; and a middle layer interposed between the protective film and the display panel, wherein the middle layer has a light-blocking area and a light-transmitting area, the light-blocking area overlaps with the display area, and the light-transmitting area overlaps with the pad area.

Abstract: An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.