Abstract: A method for producing a micromechanical device having inclined optical windows, and a corresponding micromechanical device are described. The production method includes: providing a first substrate having a front side and a rear side; forming a plurality of spaced-apart through holes in the first substrate which are arranged along a plurality of spaced-apart rows in the first substrate; forming a respective continuous beveled groove along each of the rows, the grooves defining a seat for the inclined optical windows; and inserting the optical windows into the grooves above the through holes.

Abstract: A display device includes: a display area including a plurality of pixels; a first peripheral area disposed at one side of the display area; and a second peripheral area disposed at the opposite side of the display area, wherein a first column spacer is disposed in the display area, a second column spacer is disposed in the first peripheral area, and a third column spacer is disposed in the second peripheral area. The patterns of an exposure mask utilized in the first peripheral area in which the second column spacer is disposed and the second peripheral area in which the third column spacer is disposed may be different from each other.

Abstract: A method of forming a bipolar transistor with a vertical collector contact requires providing a transistor comprising a plurality of epitaxial semiconductor layers on a first substrate, and providing a host substrate. A metal collector contact is patterned on the top surface of the host substrate, and the plurality of epitaxial semiconductor layers is transferred from the first substrate onto the metal collector contact on the host substrate. The first substrate is suitably the growth substrate for the plurality of epitaxial semiconductor layers. The host substrate preferably has a higher thermal conductivity than does the first substrate, which improves the heat dissipation characteristics of the transistor and allows it to operate at higher power densities. A plurality of transistors may be transferred onto a common host substrate to form a multi-finger transistor.

Abstract: A semiconductor device structure and a method for fabricating the semiconductor device structure are disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin.

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

Abstract: An object is to provide a technique capable of suppressing reduction in sticking force of a semiconductor package and a radiation fin in a semiconductor device including the semiconductor package and the radiation fin when the semiconductor package and the radiation fin stick and are fixed to each other by magnetic force. A semiconductor device includes: a semiconductor package; an insulating substrate; a radiation fin; a first fixed part made up of one of a magnetic body and a bond magnet integrally formed with the semiconductor package; and a second fixed part made up of another one of the magnetic body and the bond magnet integrally formed with the radiation fin, wherein the semiconductor package and the radiation fin stick to each other by magnetic force occurring between the first fixed part and the second fixed part.

Abstract: An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.

Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

Abstract: A cavity type semiconductor package with a substrate and a cap is disclosed. The semiconductor package includes a first semiconductor die coupled to the substrate and a layer of flexible material on a surface of the cap. A trace is on the layer of flexible material. The cap is coupled to the substrate with the layer of flexible material and the trace between the cap and the substrate. A second semiconductor die is coupled to the layer of flexible material and the trace on the cap. The cap further includes an aperture to expose the second semiconductor die to the ambient environment. The layer of flexible material absorbs stress during operation cycles of the package induced by the different coefficient of thermal expansions of the cap and the substrate to reduce the likelihood of separation of the cap from the substrate.

Abstract: A multi-layered piezoelectric ceramic-containing structure There is provided a multi-layered piezoelectric ceramic-containing structure comprising: a metal substrate; a metallic adhesive layer on a surface of the metal substrate; a non-metallic thermal barrier layer on the metallic adhesive layer; and a piezoelectric ceramic layer sandwiched between a first electrode layer and a second electrode layer, wherein the first electrode layer is on the non-metallic thermal barrier layer. There is also provided a method of forming the structure.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a base, a first insulating layer disposed above the base, a first alignment pattern disposed in the peripheral area on a surface of the first insulating layer facing away from the base, and a second alignment pattern disposed in the peripheral area at a side of the first insulating layer away from the base. An orthographic projection of the second alignment pattern on the base and an orthographic projection of the first alignment pattern on the base have a non-overlapping region therebetween, and the second alignment pattern is in contact with the first insulating layer in the non-overlapping region. Adhesion between the second alignment pattern and the first insulating layer is greater than adhesion between the second alignment pattern and the first alignment pattern.

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

Abstract: An open circuit voltage photodetector comprises a photovoltaic device including a photovoltaic junction, and a transistor. The photovoltaic device is connected to the gate terminal of the transistor to input an open circuit voltage of the photovoltaic device to the gate terminal. An array of such photodetectors and a readout integrated circuit forms an image sensor. In a photodetection method, an open circuit voltage is generated in a photovoltaic device in response to illumination by incident radiation, and the open circuit voltage is applied to a gate terminal of a transistor to modulate a channel current flowing in a channel of the transistor. A readout electronic circuit may be fabricated with an extra transistor, and a photovoltaic device disposed on the readout electronic circuit and electrically connected to apply an open circuit voltage of the photovoltaic device to a gate of the extra transistor.

Abstract: A light emitting device includes: a base body including two conductive members, a resin body, and a fiber member placed inside the resin body, and a light-emitting element. The resin body includes an isolation section located between the two conductive members, and includes a pair of sandwiching portions sandwiching the isolation section. The fiber member has a length which is greater than a distance between the two conductive members, and is located at least in an adjoining region of at least one of the pair of sandwiching portions, the adjoining region adjoining the isolation section. In the adjoining region, the fiber member extends in a direction which is non-orthogonal to a direction in which that the pair of sandwiching portions extend.

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

Abstract: The present disclosure provides a domain wall magnetic tunnel junction device. Integration of input spikes pushes a domain wall within a ferromagnetic track toward a magnetic tunnel junction (MTJ). An energy gradient within the track pushes the domain wall away from the MTJ by leaking accumulated energy from the input spikes. If the integrated input spikes exceed the energy leak of the gradient within a specified time period, the domain wall reaches the MTJ and reverses its resistance, producing an output spike. The leaking energy gradient can be created by a magnetic field, a trapezoidal shape of the ferromagnetic track, or nonuniform material properties in the ferromagnetic track.

Abstract: A method for producing a micromechanical device having a damper structure. The method includes: (A) providing a micromechanical wafer having a rear side; (B) applying a liquid damper material onto the rear side; (C) pressing a matrix against the rear side in order to form at least one damper structure in the damper material; (D) curing the damper material; and (E) removing the matrix.

Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.

Abstract: An actuator assembly includes a primary electrode, a secondary electrode overlapping at least a portion of the primary electrode, and an electroactive polymer layer disposed between the primary electrode and the secondary electrode, where the electroactive polymer layer includes a non-vertical (e.g., sloped) sidewall with respect to a major surface of at least one of the electrodes. The electroactive polymer layer may be characterized by a non-axisymmetric shape with respect to an axis that is oriented orthogonal to an electrode major surface.

Abstract: A light emitting device includes a light emitting element having an emission peak wavelength in a range of 380 nm to 420 nm and a fluorescent member including at least one fluorescent material that is excited by light from the light emitting element for light emission, wherein a mixture of light from the light emitting element and light from the fluorescent material has a correlated color temperature in a range of 2000 K to 7500 K as measured according to JIS Z8725, and the light emitting device has a spectral distribution in which, when the integral value over a wavelength range of 380 nm to 780 nm is normalized to 100%, the proportion of an integral value over a wavelength range of 380 nm to 420 nm is 15% or more, and the ratio a as defined by the expression (1) is 0.9 or more and 1.6 or less.