Abstract: In accordance with one component, a power field effect transistor is proposed, including a substrate, a channel, a gate electrode, and a gate insulator. The gate insulator is arranged at least partly between the gate electrode and the channel and includes a material having a hysteresis with respect to its polarization, such that a switching state of the transistor produced by a voltage applied to the gate electrode is maintained after the voltage has been switched off. Furthermore, a half-bridge circuit is proposed, including a high-side transistor in accordance with the construction according to the disclosure, and a low-side transistor, and also methods and circuits for driving.

Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.

Abstract: An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench.

Abstract: According to one embodiment, a semiconductor light-emitting device includes a first electrode and a second electrode provided on the same side of a semiconductor layer. A first insulating film covers the first electrode and the second electrode. Openings in the first insulating film expose portions of the first electrode and the second electrode. Wiring portions are respectively provided on the first insulating film and in the openings in the first insulating films. A first wiring portion is connected to the first electrode and a second wiring portion is connected to the second electrode. A second insulating film is provided between a first wiring portion and a second wiring portion, with a portion of the second insulating film being provided in a gap between the first insulating film and the first wiring portion.

Abstract: Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type FinFETs and p-type FinFETs. Each of first source/drain contact structures for the n-type FinFETs includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type FinFETs includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion.

Abstract: A semiconductor device includes a first semiconductor layer having a first conductive type; a circuit layer including a second semiconductor layer; and a plurality of layered members. Each of the layered members includes an interlayer insulation film and a wiring layer formed on the interlayer insulation film. The second semiconductor layer includes a circuit element. The layered members form a multilayer wiring layer. The semiconductor device further includes a penetrating conductive member; a conductive portion; and a first conductive type region. The penetrating conductive member penetrates from the first semiconductor layer to the interlayer insulation film of the layered member at the highest position. The conductive portion includes an electrode formed in the wiring layer of the layered member at the highest position and connected to the penetrating conductive member. The first conductive type region has an impurity concentration greater than that of the first semiconductor layer.

Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

Abstract: A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer, N-drift layer and N-type CS layer within the N-drift layer near the top side. Multiple trench structures are formed by polysilicon core and gate oxide layer near the front side. There are active cells and plugged cells on top of the device. The polysilicon cores of the trenches in the active cells are connected to the gate electrode, and the polysilicon cores of the trenches in the plugged cells are connected to the emitter electrode. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and plugged cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in plugged cells are divided by N-drift layer, forming discontinuous P-type regions along the direction of trenches.

Abstract: To provide an oxide semiconductor film having stable electric conductivity and a highly reliable semiconductor device having stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film contains indium (In), gallium (Ga), and zinc (Zn) and includes a c-axis-aligned crystalline region aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed. Further, the composition of the c-axis-aligned crystalline region is represented by In1+?Ga1-?O3(ZnO)m (0<?<1 and m=1 to 3 are satisfied), and the composition of the entire oxide semiconductor film including the c-axis-aligned crystalline region is represented by InxGayO3(ZnO)m (0<x<2, 0<y<2, and m=1 to 3 are satisfied).

Abstract: An apparatus that includes a varactor element and an integrated micro-discharge source is disclosed herein. In a general embodiment, the apparatus includes at least one np junction and at least one voltage source that is configured to apply voltage across the np junction. The apparatus further includes an aperture that extends through the np junction. When the voltage is applied across the np junction, gas in the aperture is ionized, forming a plasma, in turn causing a micro-discharge (of light, charge particles, and space charge) to occur. The light (charge particles, and space charge) impinges upon the surface of the np junction exposed in the aperture, thereby altering capacitance of the np junction. When used within an oscillator circuit, the effect of the plasma on the np-junction extends the capacitance changes of the np-junction and extends the oscillator frequency range in ways not possible by a conventional voltage controlled oscillator (VCO).

Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

Abstract: A junction barrier Schottky diode is formed by shifting second semiconductor regions of a second conductivity type in a staggered shape in a first semiconductor region of a first conductivity type so that pn junction regions are formed at predetermined distances between the second semiconductor regions and the first semiconductor region. A third semiconductor region of the first conductivity type is formed between the second semiconductor regions in order to form a Schottky junction region. An electrode is formed on the second and third semiconductor regions. The second semiconductor regions arranged at equal distances in an X direction are formed in a plurality of columns in a Y direction. An amount of shift between adjacent columns in the X direction is set such that a Y-direct ion distance between the second semiconductor regions in the different columns is larger than an X-direction distance between the second semiconductor regions in each column.

Abstract: A method for manufacturing a micromechanical system includes creating a sacrificial layer at a substrate surface. A structural material is deposited at a sacrificial layer surface and at a support structure for later supporting the structural material. At least one hole is created in the structural material extending from an exposed surface of the structural material to the surface of the sacrificial layer. The at least one hole leads to a margin region of the sacrificial layer. The sacrificial layer is removed using a removal process through the at least one hole, to obtain a cavity between the surface of the substrate and the structural material. The method also includes filling the at least one hole and a portion of the cavity beneath the at least one hole close to the cavity. A corresponding micromechanical system and a microelectromechanical transducer are also described.

Abstract: Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.

Abstract: A system including first and second plurality of conductors stacked along a first axis on a substrate. The first axis is perpendicular to a plane on which the substrate lies. In the first and second plurality of conductors, each conductor is connected to an adjacent conductor by one or more first vias arranged along the first axis. The first and second plurality of conductors are arranged in parallel along a second axis (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The first plurality of conductors respectively lie on a plurality of planes (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The second plurality of conductors respectively lie on the plurality of planes. Capacitances are formed along the plurality of planes between the first plurality of conductors and the second plurality of conductors.

Abstract: Methods for temporary bussing of semiconductor package substrates are disclosed and may include metal plating regions of a packaging substrate utilizing a plurality of bussed traces, which may be decoupled by forming debuss holes at intersections of the bussed traces. The decoupled traces may then be electrically tested, and the packaging substrate may be singulated into a plurality of substrates utilizing a sawing process through singulation areas in the packaging substrate. The traces may be electrically coupled via plating bars in the substrate. The plating bars may be located in the singulation areas. The intersections of the bussed traces may be in a Y pattern, which may be repeated along the singulation areas. The debuss holes may be formed utilizing mechanical drilling or lasing. The regions of the packaging substrate may be metal plated utilizing an electroplating process. The plurality of bussed traces may be biased for the electroplating process.

Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact electrically coupled with the terminal. A first element has a first surface facing the first surface of the substrate, a first conductor at the first surface and a second conductor at a second surface. An interconnect structure may extend through the first element electrically coupling the first and second conductors. An adhesive layer may bond first surfaces of the first element and the substrate, and at least portions of the first conductor and the substrate conductor may be beyond an edge of the adhesive layer. A continuous electroless plated metal region may extend between the first conductor and the substrate conductor.

Abstract: A cross-domain electrostatic protection device having four embedded silicon controlled rectifiers (a QSCR structure) embedded in a single cell. Two grounded-gate NMOS transistors are embedded into the cross-domain electrostatic protection device for reducing trigger voltage of the QSCR structure. Furthermore, an external trigger circuit and a bias circuit are applied to the cross-domain electrostatic protection device to reduce trigger voltage of the QSCR structure and leakage current.

Abstract: An array-type light-receiving device includes a substrate including a main surface, a rear surface, and a plurality of recesses formed in the rear surface, the rear surface including an incident plane on which incident light is received; a stacked semiconductor layer disposed on the main surface of the substrate, the stacked semiconductor layer including a light-receiving layer; and a plurality of pixel regions each of which includes the light-receiving layer. The plurality of recesses are each depressed from the rear surface in a thickness direction of the substrate. In addition, each of the plurality of recesses has a bottom surface and a side surface, the bottom surface facing at least one of the plurality of pixel regions, the side surface including a tapered region inclined at a predetermined inclination angle with respect to an in-plane direction of the main surface.