Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract: A sub word line driver of a semiconductor memory device including a sub word line driver is disclosed. The sub word line driver of a semiconductor memory device comprising: a semiconductor substrate including an active region extended in a first direction; a plurality of gate electrodes extended in a second direction perpendicular to the active region; first and second metal contacts formed over the active region between the gate electrodes; a plurality of metal pads coupled to the first metal contacts; and a plurality of metal signal lines coupled to the second metal contacts, extended in the second direction, and bent at specific parts adjacent to the metal pads.

Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a gate where at least a portion of the gate is filled in a semiconductor substrate including an active region defined by an isolation layer; a junction which is disposed over the active region at both side of the gate and includes a metal-containing layer and a first semiconductor layer doped with an impurity and interposed between the active region and the metal-containing layer; and a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer and defines an opening for coupling the junction to the active region.

Abstract: A method for manufacturing a metal oxide TFT device is provided. The method includes: selecting a substrate and forming a gate electrode on a first side of the substrate; sequentially depositing an insulating layer, a semiconductor layer, and a photoresist layer on the gate electrode; using the gate electrode as a photomask, exposing from a second side of the substrate and reserving the photoresist layer aligning to the gate electrode; depositing an electrode layer on the semiconductor layer and the reserved photoresist layer; stripping the reserved photoresist layer and lifting off the electrode layer stacked on the reserved photoresist layer; etching a part of the reserved electrode layer and the semiconductor layer, and forming a source electrode, a drain electrode, and a semiconductor island. The method realizes a self-alignment using the gate electrode as the photomask when forming the source, drain electrodes and the channel. Therefore, the manufacturing processes become simple and more accurate.

Abstract: A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.

Abstract: A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.

Abstract: A memory device is disclosed. The memory device includes a substrate, including a substrate, including a source region and a drain region; and a gate stack, formed over a surface of the substrate, wherein the gate stack includes: a tunneling layer; a first layer; a second layer; a third layer; and a blocking layer; wherein each of the tunneling layer and the blocking layer has an oxygen proportion higher than the first, the second and the third layers; the first layer has a highest silicon proportion among the first, the second and the third layers; the second layer has a highest oxygen proportion among the first, the second and the third layers; and the first layer has a highest nitrogen proportion among the first, the second and the third layers. An associated gate stack and a manufacturing method are also disclosed.

Abstract: There is provided an organic EL display unit having superior light emission efficiency and superior display performance. This display unit includes two or more kinds of organic light-emitting devices, each of the organic light-emitting devices having a laminated configuration in which a first electrode layer, an organic layer, and a second electrode layer are laminated in order on a base, and the organic light-emitting devices configured to emit light of different colors. The organic layer includes a common light-emitting layer and an individual light-emitting layer, the common light-emitting layer shared by all of the kinds of organic light-emitting devices, and the individual light-emitting layer provided in only a kind configured to emit specific color light of the kinds of organic light-emitting devices. Some of the kinds of organic light-emitting devices each include a transparent conductive layer between the first electrode layer and the organic layer.

Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.

Abstract: Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness Tw sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

Abstract: A vertically oriented BARITT diode is formed in an integrated circuit. The BARITT diode has a source proximate to the top surface of the substrate of the integrated circuit, a drift region immediately below the source in the semiconductor material of the substrate, and a collector in the semiconductor material of the substrate immediately below the drift region. A dielectric isolation structure laterally surrounds the drift region, extending from the source to the collector. The source may optionally include a silicon germanium layer or may optionally include a schottky barrier contact.

Abstract: Various embodiments provide SCR ESD protection devices and methods for forming the same. An exemplary device includes a semiconductor substrate having a P-type well region, an N-type well region adjacent to the P-type well region, a first P-type doped region and a first N-type doped region in the P-type well region, and a second N-type doped region and a second P-type doped region in the N-type well region. A first center-doped region and a second center-doped region doped with impurity ions of a same type are located between the first N-type doped region and the second P-type doped region and extend across the P-type well region and the N-type well region. The first center-doped region is located within the second center-doped region, has a doping concentration higher than a doping concentration in the second center-doped region, and has a depth smaller than a depth of the second center-doped region.

Abstract: An electronic chip including an integrated circuit arranged a face of a substrate, and a protection device arranged partially facing the integrated circuit is provided. The protection device includes a capacitor having a first electrode and a second electrode between which a layer of phase change material is disposed changing locally from a first resistive state to a second resistive state different from the first state by penetration of a beam. The first state is an amorphous state wherein the capacitor has a first capacitance and/or a first resistance and the second state is a crystalline state wherein the capacitor has a second capacitance and/or a second resistance different from the first capacitance and first resistance. The protection device is electrically connected to the integrated circuit by at least one of the first or second electrodes so that the integrated circuit measures the resistance and/or capacitance of the capacitor.

Abstract: In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.

Abstract: An exemplary light emitting diode includes a substrate; a first light emitting cell and a second light emitting cell disposed over the substrate and separated from each other; and an interconnection electrically connecting the first light emitting cell to the second light emitting cell. Each of the first and second light emitting cells includes a first conductive-type semiconductor layer, a second conductive-type semiconductor layer disposed over the first conductive-type semiconductor layer, and an active layer disposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer. At least one of the first light emitting cell and the second light emitting cell includes a side surface inclined with respect to the substrate. The side surface includes a first inclined portion forming an acute angle with respect to the substrate, a second inclined portion forming an obtuse angle with respect to the substrate, and an inclination discontinuity section.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device includes gate structures within a semiconductor substrate, a shielding structure within the semiconductor substrate that includes a first portion underlying a first gate structure and a second portion proximate an end of the gate structures, and a conductive structure overlying the second portion of the shielding structure and an end region of the semiconductor substrate. The conductive structure provides an electrical connection between the second portion of the shielding structure and the end region of the semiconductor substrate residing between the gate structures proximate the end of the gate structures.

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.

Abstract: A light emitting diode (LED) chip includes a first semiconductor layer, a first light emitting layer formed on the first semiconductor layer, a second light emitting layer formed on the first light emitting layer, and a second semiconductor layer formed on the second light emitting layer. The first light emitting layer emits light having a first color. The second light emitting layer emits light having a second color different from the first color.

Abstract: The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10, and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10. The first resin molding 40 has the recess 40c comprising the bottom surface 40a and the side surface 40b formed therein, and the second resin molding 50 is placed in the recess 40c.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.