Abstract: A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer and N? drift layer. There are active cells and dummy cells on top of the device. The active cell and dummy cell are separated by gate trench. The gate trench is formed by polysilicon and gate oxide layer. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and dummy cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in dummy cells are discontinuous and electrically floating.

Abstract: Disclosed herein is an OLED (Organic Light Emitting Display) device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel. A second pixel is adjacent to the first pixel in the direction in which data lines are extended. A switching thin-film transistor configured to be an LTPS (Low Temperature Poly-Silicon) thin-film transistor is disposed in the second pixel. The switching thin-film transistor of the first pixel and the switching thin-film transistor of the second pixel are connected to the same gate line. A pixel and another pixel adjacent to the pixel connected to a gate line in common, so that it is possible to provide an OLED device with high aperture ratio and high resolution.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region.

Abstract: The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes receiving a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

Abstract: A display device includes red, blue, green, and white pixels, a plurality of gate lines, a plurality of data lines, and a plurality of storage electrodes lines. Each of the red, blue, green, and white pixels includes first to third thin film transistors, a first subpixel electrode connected to an output terminal of the first thin film transistor, and a second subpixel electrode connected to the output terminal of the second thin film transistor. A channel width of a third thin film transistor in each of the red and green pixels is larger than that of a third thin film transistor in each of the blue and white pixels, or a channel length of the third thin film transistor in each of the red and green pixels is longer than that of the third thin film transistor in each of the blue and white pixels.

Abstract: A liquid crystal display device with an increased pixel aperture ratio is provided. A liquid crystal display device that displays an image with high contrast and high luminance is provided. The liquid crystal display device includes a first pixel electrode; a second pixel electrode; a transistor; a capacitor; a first insulating film; a second insulating film; and a third insulating film. The transistor includes a gate electrode; a gate insulating film; a first oxide semiconductor film; and a source electrode and a drain electrode. One of a pair of electrodes of the capacitor includes a second oxide semiconductor film. The first insulating film is provided over the first oxide semiconductor film. The second insulating film is provided over the second oxide semiconductor film such that the second oxide semiconductor film is sandwiched between the first insulating film and the second insulating film. The third insulating film overlaps with an end of the first pixel electrode.

Abstract: A light-emitting device including a light-emitting diode and a surface-modified luminophore. The surface-modified luminophore includes a luminophore including a manganese activator and a fluorine compound fixed to the luminophore.

Abstract: A method for fabricating a semiconductor structure and a solid precursor delivery system for a semiconductor fabrication is provided, the method including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film.

Abstract: A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.

Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.

Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.

Abstract: A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping oxide layer, the patterning layer leaving exposed regions of the doping oxide layer; performing a sputtering process to the substrate; and after the sputtering process, performing a wet etching process to the semiconductor substrate to remove the doping oxide layer from the exposed regions.

Abstract: A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.

Abstract: A semiconductor wafer is provided. The semiconductor wafer includes a base layer having an active region and an edge region. A number of semiconductor devices is formed on the active region. The semiconductor wafer also includes a wafer identification. The wafer identification is formed on the edge region and used for identifying the semiconductor wafer. The semiconductor wafer further includes an alignment mark. The alignment mark is formed on the edge region and is used for performing an alignment process of the semiconductor wafer.

Abstract: A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.

Abstract: A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.